Update SpinalHDL to 1.7.3

franktaTian · Sep 20, 2022 · f0e74d7 · f0e74d7
1 parent 3314d45
commit f0e74d7
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Showing 4 changed files with 5 additions and 11 deletions.
diff --git a/build.sbt b/build.sbt
@@ -2,7 +2,7 @@ name := "Proteus"
 version := "0.1"
 
 scalaVersion := "2.11.12"
-val spinalVersion = "1.6.0"
+val spinalVersion = "1.7.3"
 
 fork := true
 

diff --git a/src/main/scala/riscv/Stage.scala b/src/main/scala/riscv/Stage.scala
@@ -128,12 +128,6 @@ class Stage(val stageName: String) extends Component {
     * connection even when output() is called inside a conditional statement.
     */
   private def reworkOutsideConditionScope[T](rtl: => T) = {
-    val body = Component.current.dslBody
-    body.push()
-    val swapContext = body.swap()
-    val ret = rework(rtl)
-    body.pop()
-    swapContext.appendBack()
-    ret
+    Utils.outsideConditionScope(rework(rtl))
   }
 }
diff --git a/src/main/scala/riscv/Utils.scala b/src/main/scala/riscv/Utils.scala
@@ -38,10 +38,10 @@ object Utils {
 
   def outsideConditionScope[T](rtl: => T): T = {
     val body = Component.current.dslBody
-    body.push()
+    val ctx = body.push()
     val swapContext = body.swap()
     val ret = rtl
-    body.pop()
+    ctx.restore()
     swapContext.appendBack()
     ret
   }

diff --git a/src/main/scala/riscv/plugins/RiscvFormal.scala b/src/main/scala/riscv/plugins/RiscvFormal.scala
@@ -132,7 +132,7 @@ class RiscvFormal(altops: Boolean = false) extends Plugin[Pipeline] with FormalS
         prevRvfi := currentRvfi
       }
 
-      val rvfi = out(new Rvfi).keep()
+      val rvfi = out(new Rvfi).dontSimplifyIt()
       rvfi := prevRvfi
       rvfi.pc_wdata.allowOverride
       rvfi.pc_wdata := currentRvfi.pc_rdata