AArch64: Implement vector masked reduction evaluators

Refactor vector reduction operation evaluators to use a common helper function to reduce boilerplate code. Implement vector masked reduction operation evaluators using the same approach as non-masked ones. Signed-off-by: Akira Saitoh <[email protected]>
eclipse · Oct 21, 2022 · 8bea295 · 8bea295
1 parent a0d15d2
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diff --git a/compiler/aarch64/codegen/OMRCodeGenerator.cpp b/compiler/aarch64/codegen/OMRCodeGenerator.cpp
@@ -651,9 +651,13 @@ bool OMR::ARM64::CodeGenerator::getSupportsOpCodeForAutoSIMD(TR::CPU *cpu, TR::I
       case TR::vmin:
       case TR::vmax:
       case TR::vreductionAdd:
+      case TR::vmreductionAdd:
       case TR::vreductionMul:
+      case TR::vmreductionMul:
       case TR::vreductionMax:
+      case TR::vmreductionMax:
       case TR::vreductionMin:
+      case TR::vmreductionMin:
       case TR::vmadd:
       case TR::vmsub:
       case TR::vmmul:
@@ -674,8 +678,11 @@ bool OMR::ARM64::CodeGenerator::getSupportsOpCodeForAutoSIMD(TR::CPU *cpu, TR::I
       case TR::vxor:
       case TR::vnot:
       case TR::vreductionAnd:
+      case TR::vmreductionAnd:
       case TR::vreductionOr:
+      case TR::vmreductionOr:
       case TR::vreductionXor:
+      case TR::vmreductionXor:
       case TR::vbitselect:
       case TR::vmand:
       case TR::vmor: