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Merge tag 'riscv-sophgo-dt-for-v6.10' of https://github.com/sophgo/linux
into soc/dt RISC-V Devicetrees for v6.10 Sophgo: Added sdhci support for cv18xx/duo. Added clock support for cv18xx. Added clock for uart/sdhci. Added spi support for cv18xx. Added i2c support for cv18xx. Added reserved memory node for cv1800b/duo. Signed-off-by: Chen Wang <[email protected]> * tag 'riscv-sophgo-dt-for-v6.10' of https://github.com/sophgo/linux: riscv: dts: sophgo: add reserved memory node for CV1800B riscv: dts: sophgo: use real clock for sdhci riscv: dts: sophgo: cv18xx: Add i2c devices riscv: dts: sophgo: cv18xx: Add spi devices riscv: dts: sophgo: add uart clock for Sophgo CV1800 series SoC riscv: dts: sophgo: add clock generator for Sophgo CV1800 series SoC riscv: dts: sophgo: add sdcard support for milkv duo Link: https://lore.kernel.org/r/MA0P287MB2822CA2DE757787D6EA3B1F8FE192@MA0P287MB2822.INDP287.PROD.OUTLOOK.COM Signed-off-by: Arnd Bergmann <[email protected]>
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@@ -4,6 +4,8 @@ | |
* Copyright (C) 2023 Inochi Amaoto <[email protected]> | ||
*/ | ||
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#include <dt-bindings/clock/sophgo,cv1800.h> | ||
#include <dt-bindings/gpio/gpio.h> | ||
#include <dt-bindings/interrupt-controller/irq.h> | ||
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/ { | ||
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@@ -53,6 +55,12 @@ | |
dma-noncoherent; | ||
ranges; | ||
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clk: clock-controller@3002000 { | ||
reg = <0x03002000 0x1000>; | ||
clocks = <&osc>; | ||
#clock-cells = <1>; | ||
}; | ||
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gpio0: gpio@3020000 { | ||
compatible = "snps,dw-apb-gpio"; | ||
reg = <0x3020000 0x1000>; | ||
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@@ -125,11 +133,67 @@ | |
}; | ||
}; | ||
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i2c0: i2c@4000000 { | ||
compatible = "snps,designware-i2c"; | ||
reg = <0x04000000 0x10000>; | ||
#address-cells = <1>; | ||
#size-cells = <0>; | ||
clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C0>; | ||
clock-names = "ref", "pclk"; | ||
interrupts = <49 IRQ_TYPE_LEVEL_HIGH>; | ||
status = "disabled"; | ||
}; | ||
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i2c1: i2c@4010000 { | ||
compatible = "snps,designware-i2c"; | ||
reg = <0x04010000 0x10000>; | ||
#address-cells = <1>; | ||
#size-cells = <0>; | ||
clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C1>; | ||
clock-names = "ref", "pclk"; | ||
interrupts = <50 IRQ_TYPE_LEVEL_HIGH>; | ||
status = "disabled"; | ||
}; | ||
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i2c2: i2c@4020000 { | ||
compatible = "snps,designware-i2c"; | ||
reg = <0x04020000 0x10000>; | ||
#address-cells = <1>; | ||
#size-cells = <0>; | ||
clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C2>; | ||
clock-names = "ref", "pclk"; | ||
interrupts = <51 IRQ_TYPE_LEVEL_HIGH>; | ||
status = "disabled"; | ||
}; | ||
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i2c3: i2c@4030000 { | ||
compatible = "snps,designware-i2c"; | ||
reg = <0x04030000 0x10000>; | ||
#address-cells = <1>; | ||
#size-cells = <0>; | ||
clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C3>; | ||
clock-names = "ref", "pclk"; | ||
interrupts = <52 IRQ_TYPE_LEVEL_HIGH>; | ||
status = "disabled"; | ||
}; | ||
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i2c4: i2c@4040000 { | ||
compatible = "snps,designware-i2c"; | ||
reg = <0x04040000 0x10000>; | ||
#address-cells = <1>; | ||
#size-cells = <0>; | ||
clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C4>; | ||
clock-names = "ref", "pclk"; | ||
interrupts = <53 IRQ_TYPE_LEVEL_HIGH>; | ||
status = "disabled"; | ||
}; | ||
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uart0: serial@4140000 { | ||
compatible = "snps,dw-apb-uart"; | ||
reg = <0x04140000 0x100>; | ||
interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; | ||
clocks = <&osc>; | ||
clocks = <&clk CLK_UART0>, <&clk CLK_APB_UART0>; | ||
clock-names = "baudclk", "apb_pclk"; | ||
reg-shift = <2>; | ||
reg-io-width = <4>; | ||
status = "disabled"; | ||
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@@ -139,7 +203,8 @@ | |
compatible = "snps,dw-apb-uart"; | ||
reg = <0x04150000 0x100>; | ||
interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; | ||
clocks = <&osc>; | ||
clocks = <&clk CLK_UART1>, <&clk CLK_APB_UART1>; | ||
clock-names = "baudclk", "apb_pclk"; | ||
reg-shift = <2>; | ||
reg-io-width = <4>; | ||
status = "disabled"; | ||
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@@ -149,7 +214,8 @@ | |
compatible = "snps,dw-apb-uart"; | ||
reg = <0x04160000 0x100>; | ||
interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; | ||
clocks = <&osc>; | ||
clocks = <&clk CLK_UART2>, <&clk CLK_APB_UART2>; | ||
clock-names = "baudclk", "apb_pclk"; | ||
reg-shift = <2>; | ||
reg-io-width = <4>; | ||
status = "disabled"; | ||
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@@ -159,22 +225,78 @@ | |
compatible = "snps,dw-apb-uart"; | ||
reg = <0x04170000 0x100>; | ||
interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; | ||
clocks = <&osc>; | ||
clocks = <&clk CLK_UART3>, <&clk CLK_APB_UART3>; | ||
clock-names = "baudclk", "apb_pclk"; | ||
reg-shift = <2>; | ||
reg-io-width = <4>; | ||
status = "disabled"; | ||
}; | ||
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spi0: spi@4180000 { | ||
compatible = "snps,dw-apb-ssi"; | ||
reg = <0x04180000 0x10000>; | ||
#address-cells = <1>; | ||
#size-cells = <0>; | ||
clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI0>; | ||
clock-names = "ssi_clk", "pclk"; | ||
interrupts = <54 IRQ_TYPE_LEVEL_HIGH>; | ||
status = "disabled"; | ||
}; | ||
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spi1: spi@4190000 { | ||
compatible = "snps,dw-apb-ssi"; | ||
reg = <0x04190000 0x10000>; | ||
#address-cells = <1>; | ||
#size-cells = <0>; | ||
clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI1>; | ||
clock-names = "ssi_clk", "pclk"; | ||
interrupts = <55 IRQ_TYPE_LEVEL_HIGH>; | ||
status = "disabled"; | ||
}; | ||
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spi2: spi@41a0000 { | ||
compatible = "snps,dw-apb-ssi"; | ||
reg = <0x041a0000 0x10000>; | ||
#address-cells = <1>; | ||
#size-cells = <0>; | ||
clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI2>; | ||
clock-names = "ssi_clk", "pclk"; | ||
interrupts = <56 IRQ_TYPE_LEVEL_HIGH>; | ||
status = "disabled"; | ||
}; | ||
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spi3: spi@41b0000 { | ||
compatible = "snps,dw-apb-ssi"; | ||
reg = <0x041b0000 0x10000>; | ||
#address-cells = <1>; | ||
#size-cells = <0>; | ||
clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI3>; | ||
clock-names = "ssi_clk", "pclk"; | ||
interrupts = <57 IRQ_TYPE_LEVEL_HIGH>; | ||
status = "disabled"; | ||
}; | ||
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uart4: serial@41c0000 { | ||
compatible = "snps,dw-apb-uart"; | ||
reg = <0x041c0000 0x100>; | ||
interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; | ||
clocks = <&osc>; | ||
clocks = <&clk CLK_UART4>, <&clk CLK_APB_UART4>; | ||
clock-names = "baudclk", "apb_pclk"; | ||
reg-shift = <2>; | ||
reg-io-width = <4>; | ||
status = "disabled"; | ||
}; | ||
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sdhci0: mmc@4310000 { | ||
compatible = "sophgo,cv1800b-dwcmshc"; | ||
reg = <0x4310000 0x1000>; | ||
interrupts = <36 IRQ_TYPE_LEVEL_HIGH>; | ||
clocks = <&clk CLK_AXI4_SD0>, | ||
<&clk CLK_SD0>; | ||
clock-names = "core", "bus"; | ||
status = "disabled"; | ||
}; | ||
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plic: interrupt-controller@70000000 { | ||
reg = <0x70000000 0x4000000>; | ||
interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>; | ||
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