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DESIGN AND VERIFICATION OF DDR SDRAM MEMORY CONTROLLER USING SYSTEMVERILOG FOR HIGHER COVERAGE

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Certificates & contents.pdf
Certificates & contents.pdf
 
 
Main report.pdf
Main report.pdf
 
 
README.md
README.md
 
 
System Verilog code
System Verilog code
 
 
Verilog codes
Verilog codes
 
 
altclklock.v
altclklock.v
 
 
configurations.sv
configurations.sv
 
 
coverage_ddr.sv
coverage_ddr.sv
 
 
ddr_base.sv
ddr_base.sv
 
 
ddr_commands.v
ddr_commands.v
 
 
ddr_controle_interface.v
ddr_controle_interface.v
 
 
ddr_data_path.v
ddr_data_path.v
 
 
ddr_drv.sv
ddr_drv.sv
 
 
ddr_dut.sv
ddr_dut.sv
 
 
ddr_env.sv
ddr_env.sv
 
 
ddr_gen.sv
ddr_gen.sv
 
 
ddr_intf.sv
ddr_intf.sv
 
 
ddr_monitor.sv
ddr_monitor.sv
 
 
ddr_score.sv
ddr_score.sv
 
 
ddr_sdram.v
ddr_sdram.v
 
 
ddr_sdram_tb.v
ddr_sdram_tb.v
 
 
ddr_tb.sv
ddr_tb.sv
 
 
ddr_tb.sv.bak
ddr_tb.sv.bak
 
 
ddr_top.sv
ddr_top.sv
 
 
mt46v4m16.v
mt46v4m16.v
 
 
params.v
params.v
 
 
pll1.v
pll1.v
 
 
pv.cr.mti
pv.cr.mti
 
 
pv.mpf
pv.mpf
 
 
reference,paper,annexure.pdf
reference,paper,annexure.pdf
 
 
transcript
transcript
 
 
vsim.wlf
vsim.wlf
 
 

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DDR-SDRAM- Verilog and System Verilog code for Design and Verificaiton

My Master Degree Thesis "DESIGN AND VERIFICATION OF DDR SDRAM MEMORY CONTROLLER USING SYSTEMVERILOG FOR HIGHER COVERAGE"

I have uploaded all the related files. please read the certificated and contents Main report and Refrence,

Then Start to look at the code for easy understanding. If you need any help, regarding this. please let me know.

Most of the source code are from the Major MNC companies. I have done the work related to system verilog for verification of the DDR SDRAM. Most of the verilog code is from the source companies. Credit and copyrights goes to them.

For SystemVerilog related coding is my own coding. If you have any queries. please let me know. thanks

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DESIGN AND VERIFICATION OF DDR SDRAM MEMORY CONTROLLER USING SYSTEMVERILOG FOR HIGHER COVERAGE

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  • Verilog 84.5%
  • SystemVerilog 15.5%