Merge branch 'remotes/lorenzo/pci/mvebu'

- Implement pci_remap_iospace() for ARM so mvebu can use
  devm_pci_remap_iospace() instead of the previous ARM-specific
  pci_ioremap_io() interface (Pali Rohár)

- Use the standard pci_host_probe() instead of the device-specific
  mvebu_pci_host_probe() (Pali Rohár)

- Replace all uses of ARM-specific pci_ioremap_io() with the
  ARM implementation of the standard pci_remap_iospace() interface and
  remove pci_ioremap_io() (Pali Rohár)

- Skip initializing invalid Root Ports (Pali Rohár)

- Check for errors from pci_bridge_emul_init() (Pali Rohár)

- Ignore any bridges at non-zero function numbers (Pali Rohár)

- Return ~0 data for invalid config read size (Pali Rohár)

- Disallow mapping interrupts on emulated bridges (Pali Rohár)

- Clear Root Port Memory & I/O Space Enable and Bus Master Enable at
  initialization (Pali Rohár)

- Make type bits in Root Port I/O Base register read-only (Pali Rohár)

- Disable Root Port windows when base/limit set to invalid values (Pali
  Rohár)

- Set controller to Root Complex mode (Pali Rohár)

- Set Root Port Class Code to PCI Bridge (Pali Rohár)

- Update emulated Root Port secondary bus numbers to better reflect the
  actual topology (Pali Rohár)

- Add PCI_BRIDGE_CTL_BUS_RESET support to emulated Root Ports so
  pci_reset_secondary_bus() can reset connected devices (Pali Rohár)

- Add PCI_EXP_DEVCTL Error Reporting Enable support to emulated Root Ports
  (Pali Rohár)

- Add PCI_EXP_RTSTA PME Status bit support to emulated Root Ports (Pali
  Rohár)

- Add DEVCAP2, DEVCTL2 and LNKCTL2 support to emulated Root Ports on Armada
  XP and newer devices (Pali Rohár)

- Export mvebu-mbus.c symbols to allow pci-mvebu.c to be a module (Pali
  Rohár)

- Add support for compiling as a module (Pali Rohár)

* remotes/lorenzo/pci/mvebu:
  PCI: mvebu: Add support for compiling driver as module
  bus: mvebu-mbus: Export symbols for public API window functions
  PCI: mvebu: Fix support for DEVCAP2, DEVCTL2 and LNKCTL2 registers on emulated bridge
  PCI: mvebu: Fix support for PCI_EXP_RTSTA on emulated bridge
  PCI: mvebu: Fix support for PCI_EXP_DEVCTL on emulated bridge
  PCI: mvebu: Fix support for PCI_BRIDGE_CTL_BUS_RESET on emulated bridge
  PCI: mvebu: Fix configuring secondary bus of PCIe Root Port via emulated bridge
  PCI: mvebu: Set PCI Bridge Class Code to PCI Bridge
  PCI: mvebu: Setup PCIe controller to Root Complex mode
  PCI: mvebu: Propagate errors when updating PCI_IO_BASE and PCI_MEM_BASE registers
  PCI: mvebu: Do not modify PCI IO type bits in conf_write
  PCI: mvebu: Fix support for bus mastering and PCI_COMMAND on emulated bridge
  PCI: mvebu: Disallow mapping interrupts on emulated bridges
  PCI: mvebu: Handle invalid size of read config request
  PCI: mvebu: Check that PCI bridge specified in DT has function number zero
  PCI: mvebu: Check for errors from pci_bridge_emul_init() call
  PCI: mvebu: Check for valid ports
  arm: ioremap: Remove unused ARM-specific function pci_ioremap_io()
  arm: ioremap: Replace pci_ioremap_io() usage by pci_remap_iospace()
  PCI: mvebu: Remove custom mvebu_pci_host_probe() function
  PCI: mvebu: Replace pci_ioremap_io() usage by devm_pci_remap_iospace()
  arm: ioremap: Implement standard PCI function pci_remap_iospace()

arch/arm/include/asm/io.h

@@ -180,7 +180,10 @@ void pci_ioremap_set_mem_type(int mem_type);
 static inline void pci_ioremap_set_mem_type(int mem_type) {}
 #endif
 
-extern int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr);
+struct resource;
+
+#define pci_remap_iospace pci_remap_iospace
+int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
 
 /*
  * PCI configuration space mapping function.

arch/arm/mach-dove/pcie.c

@@ -38,6 +38,7 @@ static int num_pcie_ports;
 static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys)
 {
 	struct pcie_port *pp;
+	struct resource realio;
 
 	if (nr >= num_pcie_ports)
 		return 0;
@@ -53,10 +54,10 @@ static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys)
 
 	orion_pcie_setup(pp->base);
 
-	if (pp->index == 0)
-		pci_ioremap_io(sys->busnr * SZ_64K, DOVE_PCIE0_IO_PHYS_BASE);
-	else
-		pci_ioremap_io(sys->busnr * SZ_64K, DOVE_PCIE1_IO_PHYS_BASE);
+	realio.start = sys->busnr * SZ_64K;
+	realio.end = realio.start + SZ_64K - 1;
+	pci_remap_iospace(&realio, pp->index == 0 ? DOVE_PCIE0_IO_PHYS_BASE :
+						    DOVE_PCIE1_IO_PHYS_BASE);
 
 	/*
 	 * IORESOURCE_MEM

arch/arm/mach-iop32x/pci.c

@@ -185,6 +185,7 @@ iop3xx_pci_abort(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
 int iop3xx_pci_setup(int nr, struct pci_sys_data *sys)
 {
 	struct resource *res;
+	struct resource realio;
 
 	if (nr != 0)
 		return 0;
@@ -206,7 +207,9 @@ int iop3xx_pci_setup(int nr, struct pci_sys_data *sys)
 
 	pci_add_resource_offset(&sys->resources, res, sys->mem_offset);
 
-	pci_ioremap_io(0, IOP3XX_PCI_LOWER_IO_PA);
+	realio.start = 0;
+	realio.end = realio.start + SZ_64K - 1;
+	pci_remap_iospace(&realio, IOP3XX_PCI_LOWER_IO_PA);
 
 	return 1;
 }

arch/arm/mach-mv78xx0/pcie.c

@@ -101,6 +101,7 @@ static void __init mv78xx0_pcie_preinit(void)
 static int __init mv78xx0_pcie_setup(int nr, struct pci_sys_data *sys)
 {
 	struct pcie_port *pp;
+	struct resource realio;
 
 	if (nr >= num_pcie_ports)
 		return 0;
@@ -115,7 +116,9 @@ static int __init mv78xx0_pcie_setup(int nr, struct pci_sys_data *sys)
 	orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
 	orion_pcie_setup(pp->base);
 
-	pci_ioremap_io(nr * SZ_64K, MV78XX0_PCIE_IO_PHYS_BASE(nr));
+	realio.start = nr * SZ_64K;
+	realio.end = realio.start + SZ_64K - 1;
+	pci_remap_iospace(&realio, MV78XX0_PCIE_IO_PHYS_BASE(nr));
 
 	pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset);
 

arch/arm/mach-orion5x/pci.c

@@ -142,6 +142,7 @@ static struct pci_ops pcie_ops = {
 static int __init pcie_setup(struct pci_sys_data *sys)
 {
 	struct resource *res;
+	struct resource realio;
 	int dev;
 
 	/*
@@ -164,7 +165,9 @@ static int __init pcie_setup(struct pci_sys_data *sys)
 		pcie_ops.read = pcie_rd_conf_wa;
 	}
 
-	pci_ioremap_io(sys->busnr * SZ_64K, ORION5X_PCIE_IO_PHYS_BASE);
+	realio.start = sys->busnr * SZ_64K;
+	realio.end = realio.start + SZ_64K - 1;
+	pci_remap_iospace(&realio, ORION5X_PCIE_IO_PHYS_BASE);
 
 	/*
 	 * Request resources.
@@ -466,6 +469,7 @@ static void __init orion5x_setup_pci_wins(void)
 static int __init pci_setup(struct pci_sys_data *sys)
 {
 	struct resource *res;
+	struct resource realio;
 
 	/*
 	 * Point PCI unit MBUS decode windows to DRAM space.
@@ -482,7 +486,9 @@ static int __init pci_setup(struct pci_sys_data *sys)
 	 */
 	orion5x_setbits(PCI_CMD, PCI_CMD_HOST_REORDER);
 
-	pci_ioremap_io(sys->busnr * SZ_64K, ORION5X_PCI_IO_PHYS_BASE);
+	realio.start = sys->busnr * SZ_64K;
+	realio.end = realio.start + SZ_64K - 1;
+	pci_remap_iospace(&realio, ORION5X_PCI_IO_PHYS_BASE);
 
 	/*
 	 * Request resources

arch/arm/mm/ioremap.c

@@ -459,16 +459,20 @@ void pci_ioremap_set_mem_type(int mem_type)
 	pci_ioremap_mem_type = mem_type;
 }
 
-int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr)
+int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr)
 {
-	BUG_ON(offset + SZ_64K - 1 > IO_SPACE_LIMIT);
+	unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
 
-	return ioremap_page_range(PCI_IO_VIRT_BASE + offset,
-				  PCI_IO_VIRT_BASE + offset + SZ_64K,
-				  phys_addr,
+	if (!(res->flags & IORESOURCE_IO))
+		return -EINVAL;
+
+	if (res->end > IO_SPACE_LIMIT)
+		return -EINVAL;
+
+	return ioremap_page_range(vaddr, vaddr + resource_size(res), phys_addr,
 				  __pgprot(get_mem_type(pci_ioremap_mem_type)->prot_pte));
 }
-EXPORT_SYMBOL_GPL(pci_ioremap_io);
+EXPORT_SYMBOL(pci_remap_iospace);
 
 void __iomem *pci_remap_cfgspace(resource_size_t res_cookie, size_t size)
 {

drivers/bus/mvebu-mbus.c

@@ -914,13 +914,15 @@ int mvebu_mbus_add_window_remap_by_id(unsigned int target,
 
 	return mvebu_mbus_alloc_window(s, base, size, remap, target, attribute);
 }
+EXPORT_SYMBOL_GPL(mvebu_mbus_add_window_remap_by_id);
 
 int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute,
 				phys_addr_t base, size_t size)
 {
 	return mvebu_mbus_add_window_remap_by_id(target, attribute, base,
 						 size, MVEBU_MBUS_NO_REMAP);
 }
+EXPORT_SYMBOL_GPL(mvebu_mbus_add_window_by_id);
 
 int mvebu_mbus_del_window(phys_addr_t base, size_t size)
 {
@@ -933,20 +935,23 @@ int mvebu_mbus_del_window(phys_addr_t base, size_t size)
 	mvebu_mbus_disable_window(&mbus_state, win);
 	return 0;
 }
+EXPORT_SYMBOL_GPL(mvebu_mbus_del_window);
 
 void mvebu_mbus_get_pcie_mem_aperture(struct resource *res)
 {
 	if (!res)
 		return;
 	*res = mbus_state.pcie_mem_aperture;
 }
+EXPORT_SYMBOL_GPL(mvebu_mbus_get_pcie_mem_aperture);
 
 void mvebu_mbus_get_pcie_io_aperture(struct resource *res)
 {
 	if (!res)
 		return;
 	*res = mbus_state.pcie_io_aperture;
 }
+EXPORT_SYMBOL_GPL(mvebu_mbus_get_pcie_io_aperture);
 
 int mvebu_mbus_get_dram_win_info(phys_addr_t phyaddr, u8 *target, u8 *attr)
 {

drivers/pci/controller/Kconfig

@@ -4,7 +4,7 @@ menu "PCI controller drivers"
 	depends on PCI
 
 config PCI_MVEBU
-	bool "Marvell EBU PCIe controller"
+	tristate "Marvell EBU PCIe controller"
 	depends on ARCH_MVEBU || ARCH_DOVE || COMPILE_TEST
 	depends on MVEBU_MBUS
 	depends on ARM