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[binutils, ARM, 12/16] Scalar Low Overhead loop instructions for Armv…
…8.1-M Mainline s patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This patch adds support to the Scalar low overhead loop instructions: LE WLS DLS We also add a new assembler resolvable relocation bfd_reloc_code_real enum for the 12-bit branch offset used in these instructions. ChangeLog entries are as follows: *** bfd/ChnageLog *** 2019-04-12 Sudakshina Das <[email protected]> * reloc.c (BFD_RELOC_ARM_THUMB_LOOP12): New. * bfd-in2.h: Regenerated. * libbfd.h: Regenerated. *** gas/ChangeLog *** 2019-04-12 Sudakshina Das <[email protected]> Andre Vieira <[email protected]> * config/tc-arm.c (operand_parse_code): Add OP_LR and OP_oLR for the LR operand and optional LR operand. (parse_operands): Add switch cases for OP_LR and OP_oLR for both type checking and value checking. (encode_thumb32_addr_mode): New entries for DLS, WLS and LE. (v8_1_loop_reloc): New helper function for handling labels for the low overhead loop instructions. (do_t_loloop): New function to encode DLS, WLS and LE. (insns): New entries for WLS, DLS and LE. (md_pcrel_from_section): New switch case for BFD_RELOC_ARM_THUMB_LOOP12. (md_appdy_fix): Likewise. (tc_gen_reloc): Likewise. * testsuite/gas/arm/armv8_1-m-tloop.s: New. * testsuite/gas/arm/armv8_1-m-tloop.d: New. * testsuite/gas/arm/armv8_1-m-tloop-bad.s: New. * testsuite/gas/arm/armv8_1-m-tloop-bad.d: New. * testsuite/gas/arm/armv8_1-m-tloop-bad.l: New. *** opcodes/ChangeLog *** 2019-04-12 Sudakshina Das <[email protected]> * arm-dis.c (print_insn_thumb32): Updated to accept new %P and %Q patterns.
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2019-04-15 Sudakshina Das <[email protected]> | ||
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* reloc.c (BFD_RELOC_ARM_THUMB_LOOP12): New. | ||
* bfd-in2.h: Regenerated. | ||
* libbfd.h: Regenerated. | ||
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2019-04-15 Sudakshina Das <[email protected]> | ||
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* reloc.c (BFD_RELOC_THUMB_PCREL_BFCSEL): New relocation. | ||
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2019-04-15 Sudakshina Das <[email protected]> | ||
Andre Vieira <[email protected]> | ||
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* config/tc-arm.c (operand_parse_code): Add OP_LR and OP_oLR | ||
for the LR operand and optional LR operand. | ||
(parse_operands): Add switch cases for OP_LR and OP_oLR for | ||
both type checking and value checking. | ||
(encode_thumb32_addr_mode): New entries for DLS, WLS and LE. | ||
(v8_1_loop_reloc): New helper function for handling labels | ||
for the low overhead loop instructions. | ||
(do_t_loloop): New function to encode DLS, WLS and LE. | ||
(insns): New entries for WLS, DLS and LE. | ||
(md_pcrel_from_section): New switch case | ||
for BFD_RELOC_ARM_THUMB_LOOP12. | ||
(md_appdy_fix): Likewise. | ||
(tc_gen_reloc): Likewise. | ||
* testsuite/gas/arm/armv8_1-m-tloop.s: New. | ||
* testsuite/gas/arm/armv8_1-m-tloop.d: New. | ||
* testsuite/gas/arm/armv8_1-m-tloop-bad.s: New. | ||
* testsuite/gas/arm/armv8_1-m-tloop-bad.d: New. | ||
* testsuite/gas/arm/armv8_1-m-tloop-bad.l: New. | ||
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2019-04-15 Sudakshina Das <[email protected]> | ||
Andre Vieira <[email protected]> | ||
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#name: Invalid Armv8.1-M Mainline Low Overhead Loop instructions | ||
#source: armv8_1-m-loloop-bad.s | ||
#as: -march=armv8.1-m.main | ||
#error_output: armv8_1-m-loloop-bad.l |
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.*: Assembler messages: | ||
.*:5: Error: operand must be LR register -- `wls r1,r2,.LB1' | ||
.*:6: Error: operand must be LR register -- `dls r2,r2' | ||
.*:7: Error: r15 not allowed here -- `dls lr,pc' | ||
.*:8: Error: branch out of range or not a multiple of 2 | ||
.*:9: Error: branch out of range or not a multiple of 2 | ||
.*:10: Error: branch out of range or not a multiple of 2 |
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.syntax unified | ||
.text | ||
.thumb | ||
foo: | ||
wls r1, r2, .LB1 | ||
dls r2, r2 | ||
dls lr, pc | ||
le lr, #4096 | ||
le #-4098 | ||
le #-4095 | ||
.LB1: | ||
mov r3, r2 |
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#name: Valid Armv8.1-M Mainline Low Overhead loop instructions | ||
#source: armv8_1-m-loloop.s | ||
#as: -march=armv8.1-m.main | ||
#objdump: -dr --prefix-addresses --show-raw-insn | ||
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.*: +file format .*arm.* | ||
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Disassembly of section .text: | ||
0[0-9a-f]+ <[^>]+> f042 c00d wls lr, r2, 0000001c <foo\+0x1c> | ||
0[0-9a-f]+ <[^>]+> f042 e001 dls lr, r2 | ||
0[0-9a-f]+ <[^>]+> f04e e001 dls lr, lr | ||
0[0-9a-f]+ <[^>]+> f00f c009 le lr, 00000000 <foo> | ||
0[0-9a-f]+ <[^>]+> f02f c00b le 00000000 <foo> | ||
0[0-9a-f]+ <[^>]+> f00f c24b le lr, fffffb84 <foo\+0xfffffb84> | ||
0[0-9a-f]+ <[^>]+> f02f c007 le 00000010 <foo\+0x10> | ||
0[0-9a-f]+ <[^>]+> 4613 mov r3, r2 | ||
#... |
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.syntax unified | ||
.text | ||
.thumb | ||
foo: | ||
.Lstart: | ||
wls lr, r2, .LB1 | ||
dls lr, r2 | ||
dls lr, lr | ||
le lr, .Lstart | ||
le .Lstart | ||
le lr, #-1172 | ||
le #-12 | ||
.LB1: | ||
mov r3, r2 |
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2019-04-15 Sudakshina Das <[email protected]> | ||
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* arm-dis.c (print_insn_thumb32): Updated to accept new %P | ||
and %Q patterns. | ||
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2019-04-15 Sudakshina Das <[email protected]> | ||
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* arm-dis.c (thumb32_opcodes): New instruction bfcsel. | ||
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