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phy: cadence: Sierra: Add PHY PCS common register configurations
Add PHY PCS common register configuration sequences for single link. Update single link PCIe register sequence accordingly. Signed-off-by: Swapnil Jakhade <[email protected]> Reviewed-by: Aswath Govindraju <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
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