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Merge tag 'nand/for-6.3' into mtd/next
NAND core changes: * Check the data only read pattern only once * Prepare the late addition of supported operation checks * Support for sequential cache reads * Fix nand_chip kdoc Raw NAND changes: * Fsl_elbc: Propagate HW ECC settings to HW * Marvell: Add missing layouts * Pasemi: Don't use static data to track per-device state * Sunxi: - Fix the size of the last OOB region - Remove an unnecessary check - Remove an unnecessary check - Clean up chips after failed init - Precompute the ECC_CTL register value - Embed sunxi_nand_hw_ecc by value - Update OOB layout to match hardware * tmio_nand: Remove driver * vf610_nfc: Use regular comments for functions SPI-NAND changes: * Add support for AllianceMemory AS5F34G04SND * Macronix: use scratch buffer for DMA operation NAND ECC changes: * Mediatek: - Add ECC support fot MT7986 IC - Add compatible for MT7986 - dt-bindings: Split ECC engine with rawnand controller
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Documentation/devicetree/bindings/mtd/mediatek,mtk-nfc.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
%YAML 1.2 | ||
--- | ||
$id: http://devicetree.org/schemas/mtd/mediatek,mtk-nfc.yaml# | ||
$schema: http://devicetree.org/meta-schemas/core.yaml# | ||
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title: MediaTek(MTK) SoCs raw NAND FLASH controller (NFC) | ||
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maintainers: | ||
- Xiangsheng Hou <[email protected]> | ||
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properties: | ||
compatible: | ||
enum: | ||
- mediatek,mt2701-nfc | ||
- mediatek,mt2712-nfc | ||
- mediatek,mt7622-nfc | ||
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reg: | ||
items: | ||
- description: Base physical address and size of NFI. | ||
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interrupts: | ||
items: | ||
- description: NFI interrupt | ||
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clocks: | ||
items: | ||
- description: clock used for the controller | ||
- description: clock used for the pad | ||
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clock-names: | ||
items: | ||
- const: nfi_clk | ||
- const: pad_clk | ||
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ecc-engine: | ||
description: device-tree node of the required ECC engine. | ||
$ref: /schemas/types.yaml#/definitions/phandle | ||
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patternProperties: | ||
"^nand@[a-f0-9]$": | ||
$ref: nand-chip.yaml# | ||
unevaluatedProperties: false | ||
properties: | ||
reg: | ||
maximum: 1 | ||
nand-on-flash-bbt: true | ||
nand-ecc-mode: | ||
const: hw | ||
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allOf: | ||
- $ref: nand-controller.yaml# | ||
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- if: | ||
properties: | ||
compatible: | ||
contains: | ||
const: mediatek,mt2701-nfc | ||
then: | ||
patternProperties: | ||
"^nand@[a-f0-9]$": | ||
properties: | ||
nand-ecc-step-size: | ||
enum: [ 512, 1024 ] | ||
nand-ecc-strength: | ||
enum: [4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36, | ||
40, 44, 48, 52, 56, 60] | ||
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- if: | ||
properties: | ||
compatible: | ||
contains: | ||
const: mediatek,mt2712-nfc | ||
then: | ||
patternProperties: | ||
"^nand@[a-f0-9]$": | ||
properties: | ||
nand-ecc-step-size: | ||
enum: [ 512, 1024 ] | ||
nand-ecc-strength: | ||
enum: [4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36, | ||
40, 44, 48, 52, 56, 60, 68, 72, 80] | ||
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- if: | ||
properties: | ||
compatible: | ||
contains: | ||
const: mediatek,mt7622-nfc | ||
then: | ||
patternProperties: | ||
"^nand@[a-f0-9]$": | ||
properties: | ||
nand-ecc-step-size: | ||
const: 512 | ||
nand-ecc-strength: | ||
enum: [4, 6, 8, 10, 12] | ||
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required: | ||
- compatible | ||
- reg | ||
- interrupts | ||
- clocks | ||
- clock-names | ||
- ecc-engine | ||
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unevaluatedProperties: false | ||
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examples: | ||
- | | ||
#include <dt-bindings/clock/mt2701-clk.h> | ||
#include <dt-bindings/interrupt-controller/arm-gic.h> | ||
#include <dt-bindings/interrupt-controller/irq.h> | ||
soc { | ||
#address-cells = <2>; | ||
#size-cells = <2>; | ||
nand-controller@1100d000 { | ||
compatible = "mediatek,mt2701-nfc"; | ||
reg = <0 0x1100d000 0 0x1000>; | ||
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>; | ||
clocks = <&pericfg CLK_PERI_NFI>, | ||
<&pericfg CLK_PERI_NFI_PAD>; | ||
clock-names = "nfi_clk", "pad_clk"; | ||
ecc-engine = <&bch>; | ||
#address-cells = <1>; | ||
#size-cells = <0>; | ||
nand@0 { | ||
reg = <0>; | ||
nand-on-flash-bbt; | ||
nand-ecc-mode = "hw"; | ||
nand-ecc-step-size = <1024>; | ||
nand-ecc-strength = <24>; | ||
partitions { | ||
compatible = "fixed-partitions"; | ||
#address-cells = <1>; | ||
#size-cells = <1>; | ||
preloader@0 { | ||
label = "pl"; | ||
read-only; | ||
reg = <0x0 0x400000>; | ||
}; | ||
android@400000 { | ||
label = "android"; | ||
reg = <0x400000 0x12c00000>; | ||
}; | ||
}; | ||
}; | ||
}; | ||
}; |
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Documentation/devicetree/bindings/mtd/mediatek,nand-ecc-engine.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
%YAML 1.2 | ||
--- | ||
$id: http://devicetree.org/schemas/mtd/mediatek,nand-ecc-engine.yaml# | ||
$schema: http://devicetree.org/meta-schemas/core.yaml# | ||
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title: MediaTek(MTK) SoCs NAND ECC engine | ||
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maintainers: | ||
- Xiangsheng Hou <[email protected]> | ||
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description: | | ||
MTK NAND ECC engine can cowork with MTK raw NAND and SPI NAND controller. | ||
properties: | ||
compatible: | ||
enum: | ||
- mediatek,mt2701-ecc | ||
- mediatek,mt2712-ecc | ||
- mediatek,mt7622-ecc | ||
- mediatek,mt7986-ecc | ||
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reg: | ||
items: | ||
- description: Base physical address and size of ECC. | ||
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interrupts: | ||
items: | ||
- description: ECC interrupt | ||
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clocks: | ||
maxItems: 1 | ||
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clock-names: | ||
const: nfiecc_clk | ||
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required: | ||
- compatible | ||
- reg | ||
- interrupts | ||
- clocks | ||
- clock-names | ||
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additionalProperties: false | ||
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examples: | ||
- | | ||
#include <dt-bindings/clock/mt2701-clk.h> | ||
#include <dt-bindings/interrupt-controller/arm-gic.h> | ||
#include <dt-bindings/interrupt-controller/irq.h> | ||
soc { | ||
#address-cells = <2>; | ||
#size-cells = <2>; | ||
bch: ecc@1100e000 { | ||
compatible = "mediatek,mt2701-ecc"; | ||
reg = <0 0x1100e000 0 0x1000>; | ||
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>; | ||
clocks = <&pericfg CLK_PERI_NFI_ECC>; | ||
clock-names = "nfiecc_clk"; | ||
}; | ||
}; |
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