forked from torvalds/linux
-
Notifications
You must be signed in to change notification settings - Fork 17
Commit
This commit does not belong to any branch on this repository, and may belong to a fork outside of the repository.
Documentation: devicetree: add qca8k binding
Add device-tree binding for ar8xxx switch families. Cc: [email protected] Signed-off-by: John Crispin <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Signed-off-by: David S. Miller <[email protected]>
- Loading branch information
Showing
1 changed file
with
89 additions
and
0 deletions.
There are no files selected for viewing
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,89 @@ | ||
* Qualcomm Atheros QCA8xxx switch family | ||
|
||
Required properties: | ||
|
||
- compatible: should be "qca,qca8337" | ||
- #size-cells: must be 0 | ||
- #address-cells: must be 1 | ||
|
||
Subnodes: | ||
|
||
The integrated switch subnode should be specified according to the binding | ||
described in dsa/dsa.txt. As the QCA8K switches do not have a N:N mapping of | ||
port and PHY id, each subnode describing a port needs to have a valid phandle | ||
referencing the internal PHY connected to it. The CPU port of this switch is | ||
always port 0. | ||
|
||
Example: | ||
|
||
|
||
&mdio0 { | ||
phy_port1: phy@0 { | ||
reg = <0>; | ||
}; | ||
|
||
phy_port2: phy@1 { | ||
reg = <1>; | ||
}; | ||
|
||
phy_port3: phy@2 { | ||
reg = <2>; | ||
}; | ||
|
||
phy_port4: phy@3 { | ||
reg = <3>; | ||
}; | ||
|
||
phy_port5: phy@4 { | ||
reg = <4>; | ||
}; | ||
|
||
switch0@0 { | ||
compatible = "qca,qca8337"; | ||
#address-cells = <1>; | ||
#size-cells = <0>; | ||
|
||
reg = <0>; | ||
|
||
ports { | ||
#address-cells = <1>; | ||
#size-cells = <0>; | ||
port@0 { | ||
reg = <0>; | ||
label = "cpu"; | ||
ethernet = <&gmac1>; | ||
phy-mode = "rgmii"; | ||
}; | ||
|
||
port@1 { | ||
reg = <1>; | ||
label = "lan1"; | ||
phy-handle = <&phy_port1>; | ||
}; | ||
|
||
port@2 { | ||
reg = <2>; | ||
label = "lan2"; | ||
phy-handle = <&phy_port2>; | ||
}; | ||
|
||
port@3 { | ||
reg = <3>; | ||
label = "lan3"; | ||
phy-handle = <&phy_port3>; | ||
}; | ||
|
||
port@4 { | ||
reg = <4>; | ||
label = "lan4"; | ||
phy-handle = <&phy_port4>; | ||
}; | ||
|
||
port@5 { | ||
reg = <5>; | ||
label = "wan"; | ||
phy-handle = <&phy_port5>; | ||
}; | ||
}; | ||
}; | ||
}; |