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spi: convert Xilinx Zynq UltraScale+ MPSoC GQSPI bindings to YAML
Convert spi for Xilinx Zynq UltraScale+ MPSoC GQSPI bindings documentation to YAML. Signed-off-by: Nobuhiro Iwamatsu <[email protected]> Reviewed-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Mark Brown <[email protected]>
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Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
%YAML 1.2 | ||
--- | ||
$id: http://devicetree.org/schemas/spi/spi-zynqmp-qspi.yaml# | ||
$schema: http://devicetree.org/meta-schemas/core.yaml# | ||
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title: Xilinx Zynq UltraScale+ MPSoC GQSPI controller Device Tree Bindings | ||
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maintainers: | ||
- Michal Simek <[email protected]> | ||
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allOf: | ||
- $ref: "spi-controller.yaml#" | ||
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properties: | ||
compatible: | ||
const: xlnx,zynqmp-qspi-1.0 | ||
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reg: | ||
maxItems: 2 | ||
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interrupts: | ||
maxItems: 1 | ||
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clock-names: | ||
items: | ||
- const: ref_clk | ||
- const: pclk | ||
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clocks: | ||
maxItems: 2 | ||
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unevaluatedProperties: false | ||
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examples: | ||
- | | ||
#include <dt-bindings/clock/xlnx-zynqmp-clk.h> | ||
soc { | ||
#address-cells = <2>; | ||
#size-cells = <2>; | ||
qspi: spi@ff0f0000 { | ||
compatible = "xlnx,zynqmp-qspi-1.0"; | ||
clocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>; | ||
clock-names = "ref_clk", "pclk"; | ||
interrupts = <0 15 4>; | ||
interrupt-parent = <&gic>; | ||
reg = <0x0 0xff0f0000 0x0 0x1000>, | ||
<0x0 0xc0000000 0x0 0x8000000>; | ||
}; | ||
}; |