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Documentation: PCI: convert endpoint/pci-test-function.txt to reST
Convert plain text documentation to reStructuredText format and add it to Sphinx TOC tree. No essential content change. Signed-off-by: Changbin Du <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Mauro Carvalho Chehab <[email protected]>
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@@ -9,3 +9,4 @@ PCI Endpoint Framework | |
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pci-endpoint | ||
pci-endpoint-cfs | ||
pci-test-function |
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@@ -1,5 +1,10 @@ | ||
PCI TEST | ||
Kishon Vijay Abraham I <[email protected]> | ||
.. SPDX-License-Identifier: GPL-2.0 | ||
================= | ||
PCI Test Function | ||
================= | ||
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:Author: Kishon Vijay Abraham I <[email protected]> | ||
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Traditionally PCI RC has always been validated by using standard | ||
PCI cards like ethernet PCI cards or USB PCI cards or SATA PCI cards. | ||
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@@ -23,65 +28,76 @@ The PCI endpoint test device has the following registers: | |
8) PCI_ENDPOINT_TEST_IRQ_TYPE | ||
9) PCI_ENDPOINT_TEST_IRQ_NUMBER | ||
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*) PCI_ENDPOINT_TEST_MAGIC | ||
* PCI_ENDPOINT_TEST_MAGIC | ||
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This register will be used to test BAR0. A known pattern will be written | ||
and read back from MAGIC register to verify BAR0. | ||
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*) PCI_ENDPOINT_TEST_COMMAND: | ||
* PCI_ENDPOINT_TEST_COMMAND | ||
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This register will be used by the host driver to indicate the function | ||
that the endpoint device must perform. | ||
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Bitfield Description: | ||
Bit 0 : raise legacy IRQ | ||
Bit 1 : raise MSI IRQ | ||
Bit 2 : raise MSI-X IRQ | ||
Bit 3 : read command (read data from RC buffer) | ||
Bit 4 : write command (write data to RC buffer) | ||
Bit 5 : copy command (copy data from one RC buffer to another | ||
RC buffer) | ||
======== ================================================================ | ||
Bitfield Description | ||
======== ================================================================ | ||
Bit 0 raise legacy IRQ | ||
Bit 1 raise MSI IRQ | ||
Bit 2 raise MSI-X IRQ | ||
Bit 3 read command (read data from RC buffer) | ||
Bit 4 write command (write data to RC buffer) | ||
Bit 5 copy command (copy data from one RC buffer to another RC buffer) | ||
======== ================================================================ | ||
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*) PCI_ENDPOINT_TEST_STATUS | ||
* PCI_ENDPOINT_TEST_STATUS | ||
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This register reflects the status of the PCI endpoint device. | ||
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Bitfield Description: | ||
Bit 0 : read success | ||
Bit 1 : read fail | ||
Bit 2 : write success | ||
Bit 3 : write fail | ||
Bit 4 : copy success | ||
Bit 5 : copy fail | ||
Bit 6 : IRQ raised | ||
Bit 7 : source address is invalid | ||
Bit 8 : destination address is invalid | ||
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*) PCI_ENDPOINT_TEST_SRC_ADDR | ||
======== ============================== | ||
Bitfield Description | ||
======== ============================== | ||
Bit 0 read success | ||
Bit 1 read fail | ||
Bit 2 write success | ||
Bit 3 write fail | ||
Bit 4 copy success | ||
Bit 5 copy fail | ||
Bit 6 IRQ raised | ||
Bit 7 source address is invalid | ||
Bit 8 destination address is invalid | ||
======== ============================== | ||
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* PCI_ENDPOINT_TEST_SRC_ADDR | ||
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This register contains the source address (RC buffer address) for the | ||
COPY/READ command. | ||
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*) PCI_ENDPOINT_TEST_DST_ADDR | ||
* PCI_ENDPOINT_TEST_DST_ADDR | ||
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This register contains the destination address (RC buffer address) for | ||
the COPY/WRITE command. | ||
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*) PCI_ENDPOINT_TEST_IRQ_TYPE | ||
* PCI_ENDPOINT_TEST_IRQ_TYPE | ||
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This register contains the interrupt type (Legacy/MSI) triggered | ||
for the READ/WRITE/COPY and raise IRQ (Legacy/MSI) commands. | ||
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Possible types: | ||
- Legacy : 0 | ||
- MSI : 1 | ||
- MSI-X : 2 | ||
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*) PCI_ENDPOINT_TEST_IRQ_NUMBER | ||
====== == | ||
Legacy 0 | ||
MSI 1 | ||
MSI-X 2 | ||
====== == | ||
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* PCI_ENDPOINT_TEST_IRQ_NUMBER | ||
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This register contains the triggered ID interrupt. | ||
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Admissible values: | ||
- Legacy : 0 | ||
- MSI : [1 .. 32] | ||
- MSI-X : [1 .. 2048] | ||
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====== =========== | ||
Legacy 0 | ||
MSI [1 .. 32] | ||
MSI-X [1 .. 2048] | ||
====== =========== |