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Merge tag 'clk-for-linus-3.12' of git://git.linaro.org/people/mturque…
…tte/linux Pull clock framework changes from Michael Turquette: "The common clk framework changes for 3.12 are dominated by clock driver patches, both new drivers and fixes to existing. A high percentage of these are for Samsung platforms like Exynos. Core framework fixes and some new features like automagical clock re-parenting round out the patches" * tag 'clk-for-linus-3.12' of git://git.linaro.org/people/mturquette/linux: (102 commits) clk: only call get_parent if there is one clk: samsung: exynos5250: Simplify registration of PLL rate tables clk: samsung: exynos4: Register PLL rate tables for Exynos4x12 clk: samsung: exynos4: Register PLL rate tables for Exynos4210 clk: samsung: exynos4: Reorder registration of mout_vpllsrc clk: samsung: pll: Add support for rate configuration of PLL46xx clk: samsung: pll: Use new registration method for PLL46xx clk: samsung: pll: Add support for rate configuration of PLL45xx clk: samsung: pll: Use new registration method for PLL45xx clk: samsung: exynos4: Rename exynos4_plls to exynos4x12_plls clk: samsung: exynos4: Remove checks for DT node clk: samsung: exynos4: Remove unused static clkdev aliases clk: samsung: Modify _get_rate() helper to use __clk_lookup() clk: samsung: exynos4: Use separate aliases for cpufreq related clocks clocksource: samsung_pwm_timer: Get clock from device tree ARM: dts: exynos4: Specify PWM clocks in PWM node pwm: samsung: Update DT bindings documentation to cover clocks clk: Move symbol export to proper location clk: fix new_parent dereference before null check clk: wm831x: Initialise wm831x pointer on init ...
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77
Documentation/devicetree/bindings/clock/samsung,s3c64xx-clock.txt
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* Samsung S3C64xx Clock Controller | ||
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The S3C64xx clock controller generates and supplies clock to various controllers | ||
within the SoC. The clock binding described here is applicable to all SoCs in | ||
the S3C64xx family. | ||
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Required Properties: | ||
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- compatible: should be one of the following. | ||
- "samsung,s3c6400-clock" - controller compatible with S3C6400 SoC. | ||
- "samsung,s3c6410-clock" - controller compatible with S3C6410 SoC. | ||
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- reg: physical base address of the controller and length of memory mapped | ||
region. | ||
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- #clock-cells: should be 1. | ||
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Each clock is assigned an identifier and client nodes can use this identifier | ||
to specify the clock which they consume. Some of the clocks are available only | ||
on a particular S3C64xx SoC and this is specified where applicable. | ||
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All available clocks are defined as preprocessor macros in | ||
dt-bindings/clock/samsung,s3c64xx-clock.h header and can be used in device | ||
tree sources. | ||
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External clocks: | ||
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There are several clocks that are generated outside the SoC. It is expected | ||
that they are defined using standard clock bindings with following | ||
clock-output-names: | ||
- "fin_pll" - PLL input clock (xtal/extclk) - required, | ||
- "xusbxti" - USB xtal - required, | ||
- "iiscdclk0" - I2S0 codec clock - optional, | ||
- "iiscdclk1" - I2S1 codec clock - optional, | ||
- "iiscdclk2" - I2S2 codec clock - optional, | ||
- "pcmcdclk0" - PCM0 codec clock - optional, | ||
- "pcmcdclk1" - PCM1 codec clock - optional, only S3C6410. | ||
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Example: Clock controller node: | ||
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clock: clock-controller@7e00f000 { | ||
compatible = "samsung,s3c6410-clock"; | ||
reg = <0x7e00f000 0x1000>; | ||
#clock-cells = <1>; | ||
}; | ||
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Example: Required external clocks: | ||
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fin_pll: clock-fin-pll { | ||
compatible = "fixed-clock"; | ||
clock-output-names = "fin_pll"; | ||
clock-frequency = <12000000>; | ||
#clock-cells = <0>; | ||
}; | ||
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xusbxti: clock-xusbxti { | ||
compatible = "fixed-clock"; | ||
clock-output-names = "xusbxti"; | ||
clock-frequency = <48000000>; | ||
#clock-cells = <0>; | ||
}; | ||
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Example: UART controller node that consumes the clock generated by the clock | ||
controller (refer to the standard clock bindings for information about | ||
"clocks" and "clock-names" properties): | ||
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uart0: serial@7f005000 { | ||
compatible = "samsung,s3c6400-uart"; | ||
reg = <0x7f005000 0x100>; | ||
interrupt-parent = <&vic1>; | ||
interrupts = <5>; | ||
clock-names = "uart", "clk_uart_baud2", | ||
"clk_uart_baud3"; | ||
clocks = <&clock PCLK_UART0>, <&clocks PCLK_UART0>, | ||
<&clock SCLK_UART>; | ||
status = "disabled"; | ||
}; |
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75
Documentation/devicetree/bindings/clock/sunxi/sun5i-a10s-gates.txt
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Gate clock outputs | ||
------------------ | ||
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* AXI gates ("allwinner,sun4i-axi-gates-clk") | ||
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DRAM 0 | ||
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* AHB gates ("allwinner,sun5i-a10s-ahb-gates-clk") | ||
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USB0 0 | ||
EHCI0 1 | ||
OHCI0 2 | ||
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SS 5 | ||
DMA 6 | ||
BIST 7 | ||
MMC0 8 | ||
MMC1 9 | ||
MMC2 10 | ||
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NAND 13 | ||
SDRAM 14 | ||
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EMAC 17 | ||
TS 18 | ||
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SPI0 20 | ||
SPI1 21 | ||
SPI2 22 | ||
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GPS 26 | ||
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HSTIMER 28 | ||
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VE 32 | ||
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TVE 34 | ||
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LCD 36 | ||
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CSI 40 | ||
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HDMI 43 | ||
DE_BE 44 | ||
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DE_FE 46 | ||
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IEP 51 | ||
MALI400 52 | ||
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* APB0 gates ("allwinner,sun5i-a10s-apb0-gates-clk") | ||
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CODEC 0 | ||
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IIS 3 | ||
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PIO 5 | ||
IR 6 | ||
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KEYPAD 10 | ||
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* APB1 gates ("allwinner,sun5i-a10s-apb1-gates-clk") | ||
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I2C0 0 | ||
I2C1 1 | ||
I2C2 2 | ||
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UART0 16 | ||
UART1 17 | ||
UART2 18 | ||
UART3 19 | ||
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Notation: | ||
[*]: The datasheet didn't mention these, but they are present on AW code | ||
[**]: The datasheet had this marked as "NC" but they are used on AW code |
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Documentation/devicetree/bindings/clock/sunxi/sun6i-a31-gates.txt
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Gate clock outputs | ||
------------------ | ||
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* AHB1 gates ("allwinner,sun6i-a31-ahb1-gates-clk") | ||
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MIPI DSI 1 | ||
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SS 5 | ||
DMA 6 | ||
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MMC0 8 | ||
MMC1 9 | ||
MMC2 10 | ||
MMC3 11 | ||
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NAND1 12 | ||
NAND0 13 | ||
SDRAM 14 | ||
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GMAC 17 | ||
TS 18 | ||
HSTIMER 19 | ||
SPI0 20 | ||
SPI1 21 | ||
SPI2 22 | ||
SPI3 23 | ||
USB_OTG 24 | ||
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EHCI0 26 | ||
EHCI1 27 | ||
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OHCI0 29 | ||
OHCI1 30 | ||
OHCI2 31 | ||
VE 32 | ||
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LCD0 36 | ||
LCD1 37 | ||
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CSI 40 | ||
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HDMI 43 | ||
DE_BE0 44 | ||
DE_BE1 45 | ||
DE_FE1 46 | ||
DE_FE1 47 | ||
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MP 50 | ||
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GPU 52 | ||
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DEU0 55 | ||
DEU1 56 | ||
DRC0 57 | ||
DRC1 58 | ||
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* APB1 gates ("allwinner,sun6i-a31-apb1-gates-clk") | ||
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CODEC 0 | ||
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DIGITAL MIC 4 | ||
PIO 5 | ||
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DAUDIO0 12 | ||
DAUDIO1 13 | ||
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* APB2 gates ("allwinner,sun6i-a31-apb2-gates-clk") | ||
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I2C0 0 | ||
I2C1 1 | ||
I2C2 2 | ||
I2C3 3 | ||
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UART0 16 | ||
UART1 17 | ||
UART2 18 | ||
UART3 19 | ||
UART4 20 | ||
UART5 21 | ||
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Notation: | ||
[*]: The datasheet didn't mention these, but they are present on AW code | ||
[**]: The datasheet had this marked as "NC" but they are used on AW code |
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