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dt-bindings: iommu: Convert msm,iommu-v0 to yaml
Convert Qualcomm IOMMU v0 implementation to yaml format. iommus part being ommited for the other bindings, as mdp4 one. Signed-off-by: David Heidelberg <[email protected]> Reviewed-by: Rob Herring (Arm) <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Will Deacon <[email protected]>
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Documentation/devicetree/bindings/iommu/qcom,apq8064-iommu.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
%YAML 1.2 | ||
--- | ||
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$id: http://devicetree.org/schemas/iommu/qcom,apq8064-iommu.yaml# | ||
$schema: http://devicetree.org/meta-schemas/core.yaml# | ||
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title: Qualcomm APQ8064 IOMMU | ||
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maintainers: | ||
- David Heidelberg <[email protected]> | ||
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description: | ||
The MSM IOMMU is an implementation compatible with the ARM VMSA short | ||
descriptor page tables. It provides address translation for bus masters | ||
outside of the CPU, each connected to the IOMMU through a port called micro-TLB. | ||
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properties: | ||
compatible: | ||
const: qcom,apq8064-iommu | ||
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clocks: | ||
items: | ||
- description: interface clock for register accesses | ||
- description: functional clock for bus accesses | ||
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clock-names: | ||
items: | ||
- const: smmu_pclk | ||
- const: iommu_clk | ||
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reg: | ||
maxItems: 1 | ||
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interrupts: | ||
description: Specifiers for the MMU fault interrupts. | ||
minItems: 1 | ||
items: | ||
- description: non-secure mode interrupt | ||
- description: secure mode interrupt (for instances which supports it) | ||
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"#iommu-cells": | ||
const: 1 | ||
description: Each IOMMU specifier describes a single Stream ID. | ||
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qcom,ncb: | ||
$ref: /schemas/types.yaml#/definitions/uint32 | ||
description: The total number of context banks in the IOMMU. | ||
minimum: 1 | ||
maximum: 4 | ||
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required: | ||
- reg | ||
- interrupts | ||
- clocks | ||
- clock-names | ||
- qcom,ncb | ||
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additionalProperties: false | ||
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examples: | ||
- | | ||
#include <dt-bindings/clock/qcom,mmcc-msm8960.h> | ||
#include <dt-bindings/interrupt-controller/irq.h> | ||
#include <dt-bindings/interrupt-controller/arm-gic.h> | ||
iommu@7500000 { | ||
compatible = "qcom,apq8064-iommu"; | ||
reg = <0x07500000 0x100000>; | ||
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, | ||
<GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; | ||
clocks = <&clk SMMU_AHB_CLK>, | ||
<&clk MDP_AXI_CLK>; | ||
clock-names = "smmu_pclk", | ||
"iommu_clk"; | ||
#iommu-cells = <1>; | ||
qcom,ncb = <2>; | ||
}; |