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Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kern…
…el/git/arm/arm-soc
Pull ARM SoC driver updates from Arnd Bergmann:
"The most noteworthy SoC driver changes this time include:
- The TEE subsystem gains an in-kernel interface to access the TEE
from device drivers.
- The reset controller subsystem gains a driver for the Qualcomm
Snapdragon 845 Power Domain Controller.
- The Xilinx Zynq platform now has a firmware interface for its
platform management unit. This contains a firmware "ioctl"
interface that was a little controversial at first, but the version
we merged solved that by not exposing arbitrary firmware calls to
user space.
- The Amlogic Meson platform gains a "canvas" driver that is used for
video processing and shared between different high-level drivers.
The rest is more of the usual, mostly related to SoC specific power
management support and core drivers in drivers/soc:
- Several Renesas SoCs (RZ/G1N, RZ/G2M, R-Car V3M, RZ/A2M) gain new
features related to power and reset control.
- The Mediatek mt8183 and mt6765 SoC platforms gain support for their
respective power management chips.
- A new driver for NXP i.MX8, which need a firmware interface for
power management.
- The SCPI firmware interface now contains support estimating power
usage of performance states
- The NVIDIA Tegra "pmc" driver gains a few new features, in
particular a pinctrl interface for configuring the pads.
- Lots of small changes for Qualcomm, in particular the "smem" device
driver.
- Some cleanups for the TI OMAP series related to their sysc
controller.
Additional cleanups and bugfixes in SoC specific drivers include the
Meson, Keystone, NXP, AT91, Sunxi, Actions, and Tegra platforms"
* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (129 commits)
firmware: tegra: bpmp: Implement suspend/resume support
drivers: clk: Add ZynqMP clock driver
dt-bindings: clock: Add bindings for ZynqMP clock driver
firmware: xilinx: Add zynqmp IOCTL API for device control
Documentation: xilinx: Add documentation for eemi APIs
MAINTAINERS: imx: include drivers/firmware/imx path
firmware: imx: add misc svc support
firmware: imx: add SCU firmware driver support
reset: Fix potential use-after-free in __of_reset_control_get()
dt-bindings: arm: fsl: add scu binding doc
soc: fsl: qbman: add interrupt coalesce changing APIs
soc: fsl: bman_portals: defer probe after bman's probe
soc: fsl: qbman: Use last response to determine valid bit
soc: fsl: qbman: Add 64 bit DMA addressing requirement to QBMan
soc: fsl: qbman: replace CPU 0 with any online CPU in hotplug handlers
soc: fsl: qbman: Check if CPU is offline when initializing portals
reset: qcom: PDC Global (Power Domain Controller) reset controller
dt-bindings: reset: Add PDC Global binding for SDM845 SoCs
reset: Grammar s/more then once/more than once/
bus: ti-sysc: Just use SET_NOIRQ_SYSTEM_SLEEP_PM_OPS
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183
Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
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| NXP i.MX System Controller Firmware (SCFW) | ||
| -------------------------------------------------------------------- | ||
|
|
||
| The System Controller Firmware (SCFW) is a low-level system function | ||
| which runs on a dedicated Cortex-M core to provide power, clock, and | ||
| resource management. It exists on some i.MX8 processors. e.g. i.MX8QM | ||
| (QM, QP), and i.MX8QX (QXP, DX). | ||
|
|
||
| The AP communicates with the SC using a multi-ported MU module found | ||
| in the LSIO subsystem. The current definition of this MU module provides | ||
| 5 remote AP connections to the SC to support up to 5 execution environments | ||
| (TZ, HV, standard Linux, etc.). The SC side of this MU module interfaces | ||
| with the LSIO DSC IP bus. The SC firmware will communicate with this MU | ||
| using the MSI bus. | ||
|
|
||
| System Controller Device Node: | ||
| ============================================================ | ||
|
|
||
| The scu node with the following properties shall be under the /firmware/ node. | ||
|
|
||
| Required properties: | ||
| ------------------- | ||
| - compatible: should be "fsl,imx-scu". | ||
| - mbox-names: should include "tx0", "tx1", "tx2", "tx3", | ||
| "rx0", "rx1", "rx2", "rx3". | ||
| - mboxes: List of phandle of 4 MU channels for tx and 4 MU channels | ||
| for rx. All 8 MU channels must be in the same MU instance. | ||
| Cross instances are not allowed. The MU instance can only | ||
| be one of LSIO MU0~M4 for imx8qxp and imx8qm. Users need | ||
| to make sure use the one which is not conflict with other | ||
| execution environments. e.g. ATF. | ||
| Note: | ||
| Channel 0 must be "tx0" or "rx0". | ||
| Channel 1 must be "tx1" or "rx1". | ||
| Channel 2 must be "tx2" or "rx2". | ||
| Channel 3 must be "tx3" or "rx3". | ||
| e.g. | ||
| mboxes = <&lsio_mu1 0 0 | ||
| &lsio_mu1 0 1 | ||
| &lsio_mu1 0 2 | ||
| &lsio_mu1 0 3 | ||
| &lsio_mu1 1 0 | ||
| &lsio_mu1 1 1 | ||
| &lsio_mu1 1 2 | ||
| &lsio_mu1 1 3>; | ||
| See Documentation/devicetree/bindings/mailbox/fsl,mu.txt | ||
| for detailed mailbox binding. | ||
|
|
||
| i.MX SCU Client Device Node: | ||
| ============================================================ | ||
|
|
||
| Client nodes are maintained as children of the relevant IMX-SCU device node. | ||
|
|
||
| Power domain bindings based on SCU Message Protocol | ||
| ------------------------------------------------------------ | ||
|
|
||
| This binding for the SCU power domain providers uses the generic power | ||
| domain binding[2]. | ||
|
|
||
| Required properties: | ||
| - compatible: Should be "fsl,scu-pd". | ||
| - #address-cells: Should be 1. | ||
| - #size-cells: Should be 0. | ||
|
|
||
| Required properties for power domain sub nodes: | ||
| - #power-domain-cells: Must be 0. | ||
|
|
||
| Optional Properties: | ||
| - reg: Resource ID of this power domain. | ||
| No exist means uncontrollable by user. | ||
| See detailed Resource ID list from: | ||
| include/dt-bindings/power/imx-rsrc.h | ||
| - power-domains: phandle pointing to the parent power domain. | ||
|
|
||
| Clock bindings based on SCU Message Protocol | ||
| ------------------------------------------------------------ | ||
|
|
||
| This binding uses the common clock binding[1]. | ||
|
|
||
| Required properties: | ||
| - compatible: Should be "fsl,imx8qxp-clock". | ||
| - #clock-cells: Should be 1. Contains the Clock ID value. | ||
| - clocks: List of clock specifiers, must contain an entry for | ||
| each required entry in clock-names | ||
| - clock-names: Should include entries "xtal_32KHz", "xtal_24MHz" | ||
|
|
||
| The clock consumer should specify the desired clock by having the clock | ||
| ID in its "clocks" phandle cell. | ||
|
|
||
| See the full list of clock IDs from: | ||
| include/dt-bindings/clock/imx8qxp-clock.h | ||
|
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||
| Pinctrl bindings based on SCU Message Protocol | ||
| ------------------------------------------------------------ | ||
|
|
||
| This binding uses the i.MX common pinctrl binding[3]. | ||
|
|
||
| Required properties: | ||
| - compatible: Should be "fsl,imx8qxp-iomuxc". | ||
|
|
||
| Required properties for Pinctrl sub nodes: | ||
| - fsl,pins: Each entry consists of 3 integers which represents | ||
| the mux and config setting for one pin. The first 2 | ||
| integers <pin_id mux_mode> are specified using a | ||
| PIN_FUNC_ID macro, which can be found in | ||
| <dt-bindings/pinctrl/pads-imx8qxp.h>. | ||
| The last integer CONFIG is the pad setting value like | ||
| pull-up on this pin. | ||
|
|
||
| Please refer to i.MX8QXP Reference Manual for detailed | ||
| CONFIG settings. | ||
|
|
||
| [1] Documentation/devicetree/bindings/clock/clock-bindings.txt | ||
| [2] Documentation/devicetree/bindings/power/power_domain.txt | ||
| [3] Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt | ||
|
|
||
| Example (imx8qxp): | ||
| ------------- | ||
| lsio_mu1: mailbox@5d1c0000 { | ||
| ... | ||
| #mbox-cells = <2>; | ||
| }; | ||
|
|
||
| firmware { | ||
| scu { | ||
| compatible = "fsl,imx-scu"; | ||
| mbox-names = "tx0", "tx1", "tx2", "tx3", | ||
| "rx0", "rx1", "rx2", "rx3"; | ||
| mboxes = <&lsio_mu1 0 0 | ||
| &lsio_mu1 0 1 | ||
| &lsio_mu1 0 2 | ||
| &lsio_mu1 0 3 | ||
| &lsio_mu1 1 0 | ||
| &lsio_mu1 1 1 | ||
| &lsio_mu1 1 2 | ||
| &lsio_mu1 1 3>; | ||
|
|
||
| clk: clk { | ||
| compatible = "fsl,imx8qxp-clk"; | ||
| #clock-cells = <1>; | ||
| }; | ||
|
|
||
| iomuxc { | ||
| compatible = "fsl,imx8qxp-iomuxc"; | ||
|
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||
| pinctrl_lpuart0: lpuart0grp { | ||
| fsl,pins = < | ||
| SC_P_UART0_RX_ADMA_UART0_RX 0x06000020 | ||
| SC_P_UART0_TX_ADMA_UART0_TX 0x06000020 | ||
| >; | ||
| }; | ||
| ... | ||
| }; | ||
|
|
||
| imx8qx-pm { | ||
| compatible = "fsl,scu-pd"; | ||
| #address-cells = <1>; | ||
| #size-cells = <0>; | ||
|
|
||
| pd_dma: dma-power-domain { | ||
| #power-domain-cells = <0>; | ||
|
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||
| pd_dma_lpuart0: dma-lpuart0@57 { | ||
| reg = <SC_R_UART_0>; | ||
| #power-domain-cells = <0>; | ||
| power-domains = <&pd_dma>; | ||
| }; | ||
| ... | ||
| }; | ||
| ... | ||
| }; | ||
| }; | ||
| }; | ||
|
|
||
| serial@5a060000 { | ||
| ... | ||
| pinctrl-names = "default"; | ||
| pinctrl-0 = <&pinctrl_lpuart0>; | ||
| clocks = <&clk IMX8QXP_UART0_CLK>, | ||
| <&clk IMX8QXP_UART0_IPG_CLK>; | ||
| clock-names = "per", "ipg"; | ||
| power-domains = <&pd_dma_lpuart0>; | ||
| }; |
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82 changes: 82 additions & 0 deletions
82
Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,82 @@ | ||
| ----------------------------------------------------------------- | ||
| Device Tree Bindings for the Xilinx Zynq MPSoC Firmware Interface | ||
| ----------------------------------------------------------------- | ||
|
|
||
| The zynqmp-firmware node describes the interface to platform firmware. | ||
| ZynqMP has an interface to communicate with secure firmware. Firmware | ||
| driver provides an interface to firmware APIs. Interface APIs can be | ||
| used by any driver to communicate to PMUFW(Platform Management Unit). | ||
| These requests include clock management, pin control, device control, | ||
| power management service, FPGA service and other platform management | ||
| services. | ||
|
|
||
| Required properties: | ||
| - compatible: Must contain: "xlnx,zynqmp-firmware" | ||
| - method: The method of calling the PM-API firmware layer. | ||
| Permitted values are: | ||
| - "smc" : SMC #0, following the SMCCC | ||
| - "hvc" : HVC #0, following the SMCCC | ||
|
|
||
| -------------------------------------------------------------------------- | ||
| Device Tree Clock bindings for the Zynq Ultrascale+ MPSoC controlled using | ||
| Zynq MPSoC firmware interface | ||
| -------------------------------------------------------------------------- | ||
| The clock controller is a h/w block of Zynq Ultrascale+ MPSoC clock | ||
| tree. It reads required input clock frequencies from the devicetree and acts | ||
| as clock provider for all clock consumers of PS clocks. | ||
|
|
||
| See clock_bindings.txt for more information on the generic clock bindings. | ||
|
|
||
| Required properties: | ||
| - #clock-cells: Must be 1 | ||
| - compatible: Must contain: "xlnx,zynqmp-clk" | ||
| - clocks: List of clock specifiers which are external input | ||
| clocks to the given clock controller. Please refer | ||
| the next section to find the input clocks for a | ||
| given controller. | ||
| - clock-names: List of clock names which are exteral input clocks | ||
| to the given clock controller. Please refer to the | ||
| clock bindings for more details. | ||
|
|
||
| Input clocks for zynqmp Ultrascale+ clock controller: | ||
|
|
||
| The Zynq UltraScale+ MPSoC has one primary and four alternative reference clock | ||
| inputs. These required clock inputs are: | ||
| - pss_ref_clk (PS reference clock) | ||
| - video_clk (reference clock for video system ) | ||
| - pss_alt_ref_clk (alternative PS reference clock) | ||
| - aux_ref_clk | ||
| - gt_crx_ref_clk (transceiver reference clock) | ||
|
|
||
| The following strings are optional parameters to the 'clock-names' property in | ||
| order to provide an optional (E)MIO clock source: | ||
| - swdt0_ext_clk | ||
| - swdt1_ext_clk | ||
| - gem0_emio_clk | ||
| - gem1_emio_clk | ||
| - gem2_emio_clk | ||
| - gem3_emio_clk | ||
| - mio_clk_XX # with XX = 00..77 | ||
| - mio_clk_50_or_51 #for the mux clock to gem tsu from 50 or 51 | ||
|
|
||
|
|
||
| Output clocks are registered based on clock information received | ||
| from firmware. Output clocks indexes are mentioned in | ||
| include/dt-bindings/clock/xlnx,zynqmp-clk.h. | ||
|
|
||
| ------- | ||
| Example | ||
| ------- | ||
|
|
||
| firmware { | ||
| zynqmp_firmware: zynqmp-firmware { | ||
| compatible = "xlnx,zynqmp-firmware"; | ||
| method = "smc"; | ||
| zynqmp_clk: clock-controller { | ||
| #clock-cells = <1>; | ||
| compatible = "xlnx,zynqmp-clk"; | ||
| clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <>_crx_ref_clk>; | ||
| clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk","aux_ref_clk", "gt_crx_ref_clk"; | ||
| }; | ||
| }; | ||
| }; |
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