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arm64: dts: qcom: sc8180x: Add remoteprocs, wifi and usb nodes
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This patch adds remoteprocs, wifi and usb and usb phy nodes
for this SoC

Co-developed-by: Bjorn Andersson <[email protected]>
Signed-off-by: Bjorn Andersson <[email protected]>
Signed-off-by: Vinod Koul <[email protected]>
Signed-off-by: Bjorn Andersson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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@vinodkoul @andersson
vinodkoul authored and andersson committed May 30, 2023
1 parent d20b6c8 commit b080f53
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355 changes: 355 additions & 0 deletions arch/arm64/boot/dts/qcom/sc8180x.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -2227,6 +2227,198 @@
wakeup-parent = <&pdc>;
};

remoteproc_mpss: remoteproc@4080000 {
compatible = "qcom,sc8180x-mpss-pas";
reg = <0x0 0x04080000 0x0 0x4040>;

interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready", "handover",
"stop-ack", "shutdown-ack";

clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";

power-domains = <&rpmhpd SC8180X_CX>,
<&rpmhpd SC8180X_MSS>;
power-domain-names = "cx", "mss";

qcom,qmp = <&aoss_qmp>;

qcom,smem-states = <&modem_smp2p_out 0>;
qcom,smem-state-names = "stop";

glink-edge {
interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
label = "modem";
qcom,remote-pid = <1>;
mboxes = <&apss_shared 12>;
};
};

remoteproc_cdsp: remoteproc@8300000 {
compatible = "qcom,sc8180x-cdsp-pas";
reg = <0x0 0x08300000 0x0 0x4040>;

interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
<&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
<&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
<&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
<&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready",
"handover", "stop-ack";

clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";

power-domains = <&rpmhpd SC8180X_CX>;
power-domain-names = "cx";

qcom,qmp = <&aoss_qmp>;

qcom,smem-states = <&cdsp_smp2p_out 0>;
qcom,smem-state-names = "stop";

status = "disabled";

glink-edge {
interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
label = "cdsp";
qcom,remote-pid = <5>;
mboxes = <&apss_shared 4>;
};
};

usb_prim_hsphy: phy@88e2000 {
compatible = "qcom,sc8180x-usb-hs-phy",
"qcom,usb-snps-hs-7nm-phy";
reg = <0 0x088e2000 0 0x400>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "ref";
resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;

#phy-cells = <0>;

status = "disabled";
};

usb_sec_hsphy: phy@88e3000 {
compatible = "qcom,sc8180x-usb-hs-phy",
"qcom,usb-snps-hs-7nm-phy";
reg = <0 0x088e3000 0 0x400>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "ref";
resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;

#phy-cells = <0>;

status = "disabled";
};

usb_prim_qmpphy: phy@88e9000 {
compatible = "qcom,sc8180x-qmp-usb3-dp-phy";
reg = <0 0x088e9000 0 0x18c>,
<0 0x088e8000 0 0x38>,
<0 0x088ea000 0 0x40>;
reg-names = "reg-base", "dp_com";
clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_USB3_PRIM_CLKREF_CLK>,
<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
clock-names = "aux",
"ref_clk_src",
"ref",
"com_aux";
resets = <&gcc GCC_USB3_DP_PHY_PRIM_SP0_BCR>,
<&gcc GCC_USB3_PHY_PRIM_SP0_BCR>;
reset-names = "phy", "common";

#clock-cells = <1>;
#address-cells = <2>;
#size-cells = <2>;
ranges;

status = "disabled";

usb_prim_ssphy: usb3-phy@88e9200 {
reg = <0 0x088e9200 0 0x200>,
<0 0x088e9400 0 0x200>,
<0 0x088e9c00 0 0x218>,
<0 0x088e9600 0 0x200>,
<0 0x088e9800 0 0x200>,
<0 0x088e9a00 0 0x100>;
#phy-cells = <0>;
clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
clock-names = "pipe0";
clock-output-names = "usb3_prim_phy_pipe_clk_src";
};

usb_prim_dpphy: dp-phy@88ea200 {
reg = <0 0x088ea200 0 0x200>,
<0 0x088ea400 0 0x200>,
<0 0x088eaa00 0 0x200>,
<0 0x088ea600 0 0x200>,
<0 0x088ea800 0 0x200>;
#clock-cells = <1>;
#phy-cells = <0>;
};
};

usb_sec_qmpphy: phy@88ee000 {
compatible = "qcom,sc8180x-qmp-usb3-dp-phy";
reg = <0 0x088ee000 0 0x18c>,
<0 0x088ed000 0 0x10>,
<0 0x088ef000 0 0x40>;
reg-names = "reg-base", "dp_com";
clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_USB3_SEC_CLKREF_CLK>,
<&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
clock-names = "aux",
"ref_clk_src",
"ref",
"com_aux";
resets = <&gcc GCC_USB3_DP_PHY_SEC_BCR>,
<&gcc GCC_USB3_PHY_SEC_BCR>;
reset-names = "phy", "common";

#clock-cells = <1>;
#address-cells = <2>;
#size-cells = <2>;
ranges;

status = "disabled";

usb_sec_ssphy: usb3-phy@88e9200 {
reg = <0 0x088ee200 0 0x200>,
<0 0x088ee400 0 0x200>,
<0 0x088eec00 0 0x218>,
<0 0x088ee600 0 0x200>,
<0 0x088ee800 0 0x200>,
<0 0x088eea00 0 0x100>;
#phy-cells = <0>;
clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
clock-names = "pipe0";
clock-output-names = "usb3_sec_phy_pipe_clk_src";
};

usb_sec_dpphy: dp-phy@88ef200 {
reg = <0 0x088ef200 0 0x200>,
<0 0x088ef400 0 0x200>,
<0 0x088efa00 0 0x200>,
<0 0x088ef600 0 0x200>,
<0 0x088ef800 0 0x200>;
#clock-cells = <1>;
#phy-cells = <0>;
clock-output-names = "qmp_dptx1_phy_pll_link_clk",
"qmp_dptx1_phy_pll_vco_div_clk";
};
};

system-cache-controller@9200000 {
compatible = "qcom,sc8180x-llcc";
reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>;
Expand All @@ -2241,6 +2433,112 @@
qcom,bcm-voters = <&apps_bcm_voter>;
};

usb_prim: usb@a6f8800 {
compatible = "qcom,sc8180x-dwc3", "qcom,dwc3";
reg = <0 0x0a6f8800 0 0x400>;
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hs_phy_irq",
"ss_phy_irq",
"dm_hs_phy_irq",
"dp_hs_phy_irq";

clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
<&gcc GCC_USB30_PRIM_MASTER_CLK>,
<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
<&gcc GCC_USB30_PRIM_SLEEP_CLK>,
<&gcc GCC_USB3_SEC_CLKREF_CLK>;
clock-names = "cfg_noc",
"core",
"iface",
"mock_utmi",
"sleep",
"xo";
resets = <&gcc GCC_USB30_PRIM_BCR>;
power-domains = <&gcc USB30_PRIM_GDSC>;

interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>;
interconnect-names = "usb-ddr", "apps-usb";

assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
assigned-clock-rates = <19200000>, <200000000>;

#address-cells = <2>;
#size-cells = <2>;
ranges;
dma-ranges;

status = "disabled";

usb_prim_dwc3: usb@a600000 {
compatible = "snps,dwc3";
reg = <0 0x0a600000 0 0xcd00>;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
iommus = <&apps_smmu 0x140 0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
phys = <&usb_prim_hsphy>, <&usb_prim_ssphy>;
phy-names = "usb2-phy", "usb3-phy";
};
};

usb_sec: usb@a8f8800 {
compatible = "qcom,sc8180x-dwc3", "qcom,dwc3";
reg = <0 0x0a8f8800 0 0x400>;

clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
<&gcc GCC_USB30_SEC_MASTER_CLK>,
<&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
<&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
<&gcc GCC_USB30_SEC_SLEEP_CLK>,
<&gcc GCC_USB3_SEC_CLKREF_CLK>;
clock-names = "cfg_noc",
"core",
"iface",
"mock_utmi",
"sleep",
"xo";
resets = <&gcc GCC_USB30_SEC_BCR>;
power-domains = <&gcc USB30_SEC_GDSC>;
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hs_phy_irq", "ss_phy_irq",
"dm_hs_phy_irq", "dp_hs_phy_irq";

assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
<&gcc GCC_USB30_SEC_MASTER_CLK>;
assigned-clock-rates = <19200000>, <200000000>;

interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>;
interconnect-names = "usb-ddr", "apps-usb";

#address-cells = <2>;
#size-cells = <2>;
ranges;
dma-ranges;

status = "disabled";

usb_sec_dwc3: usb@a800000 {
compatible = "snps,dwc3";
reg = <0 0x0a800000 0 0xcd00>;
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
iommus = <&apps_smmu 0x160 0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
phys = <&usb_sec_hsphy>, <&usb_sec_ssphy>;
phy-names = "usb2-phy", "usb3-phy";
};
};

pdc: interrupt-controller@b220000 {
compatible = "qcom,sc8180x-pdc", "qcom,pdc";
reg = <0 0x0b220000 0 0x30000>;
Expand Down Expand Up @@ -2416,6 +2714,39 @@

};

remoteproc_adsp: remoteproc@17300000 {
compatible = "qcom,sc8180x-adsp-pas";
reg = <0x0 0x17300000 0x0 0x4040>;

interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready",
"handover", "stop-ack";

clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";

power-domains = <&rpmhpd SC8180X_CX>;
power-domain-names = "cx";

qcom,qmp = <&aoss_qmp>;

qcom,smem-states = <&adsp_smp2p_out 0>;
qcom,smem-state-names = "stop";

status = "disabled";

remoteproc_adsp_glink: glink-edge {
interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
label = "lpass";
qcom,remote-pid = <2>;
mboxes = <&apss_shared 8>;
};
};

intc: interrupt-controller@17a00000 {
compatible = "arm,gic-v3";
interrupt-controller;
Expand Down Expand Up @@ -2615,6 +2946,30 @@
#clock-cells = <1>;
};

wifi: wifi@18800000 {
compatible = "qcom,wcn3990-wifi";
reg = <0 0x18800000 0 0x800000>;
reg-names = "membase";
clock-names = "cxo_ref_clk_pin";
clocks = <&rpmhcc RPMH_RF_CLK2>;
interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
iommus = <&apps_smmu 0x0640 0x1>;
qcom,msa-fixed-perm;
status = "disabled";
};
};

thermal-zones {
cpu0-thermal {
polling-delay-passive = <250>;
Expand Down

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