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clk: shmobile: Add DIV6 clock support
DIV6 clocks are divider gate clocks controlled through a single register. The divider is expressed on 6 bits, hence the name, and can take values from 1/1 to 1/64. Those clocks are found on Renesas ARM SoCs. Signed-off-by: Laurent Pinchart <[email protected]> Signed-off-by: Mike Turquette <[email protected]>
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Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt
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* Renesas CPG DIV6 Clock | ||
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The CPG DIV6 clocks are variable factor clocks provided by the Clock Pulse | ||
Generator (CPG). They clock input is divided by a configurable factor from 1 | ||
to 64. | ||
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Required Properties: | ||
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- compatible: Must be one of the following | ||
- "renesas,r8a7790-div6-clock" for R8A7790 (R-Car H2) DIV6 clocks | ||
- "renesas,r8a7791-div6-clock" for R8A7791 (R-Car M2) DIV6 clocks | ||
- "renesas,cpg-div6-clock" for generic DIV6 clocks | ||
- reg: Base address and length of the memory resource used by the DIV6 clock | ||
- clocks: Reference to the parent clock | ||
- #clock-cells: Must be 0 | ||
- clock-output-names: The name of the clock as a free-form string | ||
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Example | ||
------- | ||
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sd2_clk: sd2_clk@e6150078 { | ||
compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; | ||
reg = <0 0xe6150078 0 4>; | ||
clocks = <&pll1_div2_clk>; | ||
#clock-cells = <0>; | ||
clock-output-names = "sd2"; | ||
}; |
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obj-$(CONFIG_ARCH_R8A7790) += clk-rcar-gen2.o | ||
obj-$(CONFIG_ARCH_R8A7791) += clk-rcar-gen2.o | ||
obj-$(CONFIG_ARCH_SHMOBILE_MULTI) += clk-div6.o | ||
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# for emply built-in.o | ||
obj-n := dummy |
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/* | ||
* r8a7790 Common Clock Framework support | ||
* | ||
* Copyright (C) 2013 Renesas Solutions Corp. | ||
* | ||
* Contact: Laurent Pinchart <[email protected]> | ||
* | ||
* This program is free software; you can redistribute it and/or modify | ||
* it under the terms of the GNU General Public License as published by | ||
* the Free Software Foundation; version 2 of the License. | ||
*/ | ||
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#include <linux/clk-provider.h> | ||
#include <linux/clkdev.h> | ||
#include <linux/init.h> | ||
#include <linux/io.h> | ||
#include <linux/kernel.h> | ||
#include <linux/of.h> | ||
#include <linux/of_address.h> | ||
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#define CPG_DIV6_CKSTP BIT(8) | ||
#define CPG_DIV6_DIV(d) ((d) & 0x3f) | ||
#define CPG_DIV6_DIV_MASK 0x3f | ||
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/** | ||
* struct div6_clock - MSTP gating clock | ||
* @hw: handle between common and hardware-specific interfaces | ||
* @reg: IO-remapped register | ||
* @div: divisor value (1-64) | ||
*/ | ||
struct div6_clock { | ||
struct clk_hw hw; | ||
void __iomem *reg; | ||
unsigned int div; | ||
}; | ||
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#define to_div6_clock(_hw) container_of(_hw, struct div6_clock, hw) | ||
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static int cpg_div6_clock_enable(struct clk_hw *hw) | ||
{ | ||
struct div6_clock *clock = to_div6_clock(hw); | ||
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clk_writel(CPG_DIV6_DIV(clock->div - 1), clock->reg); | ||
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return 0; | ||
} | ||
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static void cpg_div6_clock_disable(struct clk_hw *hw) | ||
{ | ||
struct div6_clock *clock = to_div6_clock(hw); | ||
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/* DIV6 clocks require the divisor field to be non-zero when stopping | ||
* the clock. | ||
*/ | ||
clk_writel(CPG_DIV6_CKSTP | CPG_DIV6_DIV(CPG_DIV6_DIV_MASK), | ||
clock->reg); | ||
} | ||
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static int cpg_div6_clock_is_enabled(struct clk_hw *hw) | ||
{ | ||
struct div6_clock *clock = to_div6_clock(hw); | ||
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return !(clk_readl(clock->reg) & CPG_DIV6_CKSTP); | ||
} | ||
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static unsigned long cpg_div6_clock_recalc_rate(struct clk_hw *hw, | ||
unsigned long parent_rate) | ||
{ | ||
struct div6_clock *clock = to_div6_clock(hw); | ||
unsigned int div = (clk_readl(clock->reg) & CPG_DIV6_DIV_MASK) + 1; | ||
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return parent_rate / div; | ||
} | ||
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static unsigned int cpg_div6_clock_calc_div(unsigned long rate, | ||
unsigned long parent_rate) | ||
{ | ||
unsigned int div; | ||
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div = DIV_ROUND_CLOSEST(parent_rate, rate); | ||
return clamp_t(unsigned int, div, 1, 64); | ||
} | ||
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static long cpg_div6_clock_round_rate(struct clk_hw *hw, unsigned long rate, | ||
unsigned long *parent_rate) | ||
{ | ||
unsigned int div = cpg_div6_clock_calc_div(rate, *parent_rate); | ||
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return *parent_rate / div; | ||
} | ||
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static int cpg_div6_clock_set_rate(struct clk_hw *hw, unsigned long rate, | ||
unsigned long parent_rate) | ||
{ | ||
struct div6_clock *clock = to_div6_clock(hw); | ||
unsigned int div = cpg_div6_clock_calc_div(rate, parent_rate); | ||
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clock->div = div; | ||
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/* Only program the new divisor if the clock isn't stopped. */ | ||
if (!(clk_readl(clock->reg) & CPG_DIV6_CKSTP)) | ||
clk_writel(CPG_DIV6_DIV(clock->div - 1), clock->reg); | ||
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return 0; | ||
} | ||
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static const struct clk_ops cpg_div6_clock_ops = { | ||
.enable = cpg_div6_clock_enable, | ||
.disable = cpg_div6_clock_disable, | ||
.is_enabled = cpg_div6_clock_is_enabled, | ||
.recalc_rate = cpg_div6_clock_recalc_rate, | ||
.round_rate = cpg_div6_clock_round_rate, | ||
.set_rate = cpg_div6_clock_set_rate, | ||
}; | ||
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static void __init cpg_div6_clock_init(struct device_node *np) | ||
{ | ||
struct clk_init_data init; | ||
struct div6_clock *clock; | ||
const char *parent_name; | ||
const char *name; | ||
struct clk *clk; | ||
int ret; | ||
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clock = kzalloc(sizeof(*clock), GFP_KERNEL); | ||
if (!clock) { | ||
pr_err("%s: failed to allocate %s DIV6 clock\n", | ||
__func__, np->name); | ||
return; | ||
} | ||
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/* Remap the clock register and read the divisor. Disabling the | ||
* clock overwrites the divisor, so we need to cache its value for the | ||
* enable operation. | ||
*/ | ||
clock->reg = of_iomap(np, 0); | ||
if (clock->reg == NULL) { | ||
pr_err("%s: failed to map %s DIV6 clock register\n", | ||
__func__, np->name); | ||
goto error; | ||
} | ||
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clock->div = (clk_readl(clock->reg) & CPG_DIV6_DIV_MASK) + 1; | ||
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/* Parse the DT properties. */ | ||
ret = of_property_read_string(np, "clock-output-names", &name); | ||
if (ret < 0) { | ||
pr_err("%s: failed to get %s DIV6 clock output name\n", | ||
__func__, np->name); | ||
goto error; | ||
} | ||
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parent_name = of_clk_get_parent_name(np, 0); | ||
if (parent_name == NULL) { | ||
pr_err("%s: failed to get %s DIV6 clock parent name\n", | ||
__func__, np->name); | ||
goto error; | ||
} | ||
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/* Register the clock. */ | ||
init.name = name; | ||
init.ops = &cpg_div6_clock_ops; | ||
init.flags = CLK_IS_BASIC; | ||
init.parent_names = &parent_name; | ||
init.num_parents = 1; | ||
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clock->hw.init = &init; | ||
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clk = clk_register(NULL, &clock->hw); | ||
if (IS_ERR(clk)) { | ||
pr_err("%s: failed to register %s DIV6 clock (%ld)\n", | ||
__func__, np->name, PTR_ERR(clk)); | ||
goto error; | ||
} | ||
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of_clk_add_provider(np, of_clk_src_simple_get, clk); | ||
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return; | ||
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error: | ||
if (clock->reg) | ||
iounmap(clock->reg); | ||
kfree(clock); | ||
} | ||
CLK_OF_DECLARE(cpg_div6_clk, "renesas,cpg-div6-clock", cpg_div6_clock_init); |