Merge tag 'soc-newsoc-6.5' of git://git.kernel.org/pub/scm/linux/kern…

…el/git/soc/soc

Pull new ARM SoC support from Arnd Bergmann:
 "There are two new SoC families this time, and both appear fairly
  similar: The Nuvoton MA35D1 and the STMicroelectronics STM32MP2 are
  both dual-core Cortex-A35 based chips for the low-power industrial
  embedded market, and they mark the first 64-bit product in a widely
  used family of 32-bit Arm MCUs and SoCs.

  The way into the kernel is completely different here: The team at ST
  has a long history of working upstream with their STM32MP1 and other
  SoCs, and they produced a complete port to arm64 together with the
  initial announcement. Nuvoton also has multiple SoC product lines with
  current or previous upstream support, but those are maintained by
  third parties and are unrelated. The patch series from Nuvoton's Jacky
  Huang had to go through many revisisions to get to this point and is
  still missing a few drivers including the serial port for the moment.

  The branch contains the devicetree files as well as all the code
  changes, in order to have something that can be tested standalone"

* tag 'soc-newsoc-6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (25 commits)
  clk: nuvoton: Use clk_parent_data instead of string for parent clock
  clk: nuvoton: Update all constant hex values to lowercase
  clk: nuvoton: Add clk-ma35d1.h for driver extern functions
  remoteproc: stm32: use correct format strings on 64-bit
  MAINTAINERS: add entry for ARM/STM32 ARCHITECTURE
  arm64: defconfig: enable ARCH_STM32 and STM32 serial driver
  arm64: dts: st: add stm32mp257f-ev1 board support
  dt-bindings: stm32: document stm32mp257f-ev1 board
  arm64: dts: st: introduce stm32mp25 pinctrl files
  arm64: dts: st: introduce stm32mp25 SoCs family
  arm64: introduce STM32 family on Armv8 architecture
  dt-bindings: stm32: add st,stm32mp25-syscfg compatible for syscon
  pinctrl: stm32: add stm32mp257 pinctrl support
  dt-bindings: pinctrl: stm32: support for stm32mp257 and additional packages
  Documentation/process: add soc maintainer handbook
  reset: RESET_NUVOTON_MA35D1 should depend on ARCH_MA35
  reset: Add Nuvoton ma35d1 reset driver support
  clk: nuvoton: Add clock driver for ma35d1 clock controller
  arm64: dts: nuvoton: Add initial ma35d1 device tree
  dt-bindings: serial: Document ma35d1 uart controller
  ...

Documentation/devicetree/bindings/arm/nuvoton/nuvoton,ma35d1.yaml

@@ -0,0 +1,30 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/nuvoton/nuvoton,ma35d1.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Nuvoton MA35 series SoC based platforms
+
+maintainers:
+  - Jacky Huang <[email protected]>
+
+description: |
+  Boards with an ARMv8 based Nuvoton MA35 series SoC shall have
+  the following properties.
+
+properties:
+  $nodename:
+    const: '/'
+  compatible:
+    oneOf:
+
+      - description: MA35D1 based boards
+        items:
+          - enum:
+              - nuvoton,ma35d1-iot
+              - nuvoton,ma35d1-som
+          - const: nuvoton,ma35d1
+
+additionalProperties: true
+...

Documentation/devicetree/bindings/arm/npcm/npcm.yaml → Documentation/devicetree/bindings/arm/nuvoton/nuvoton,npcm.yaml

@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
 %YAML 1.2
 ---
-$id: http://devicetree.org/schemas/arm/npcm/npcm.yaml#
+$id: http://devicetree.org/schemas/arm/nuvoton/nuvoton,npcm.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
 title: NPCM Platforms

Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml

@@ -15,12 +15,13 @@ properties:
     oneOf:
       - items:
           - enum:
-              - st,stm32mp157-syscfg
-              - st,stm32mp151-pwr-mcu
-              - st,stm32-syscfg
               - st,stm32-power-config
+              - st,stm32-syscfg
               - st,stm32-tamp
               - st,stm32f4-gcan
+              - st,stm32mp151-pwr-mcu
+              - st,stm32mp157-syscfg
+              - st,stm32mp25-syscfg
           - const: syscon
       - items:
           - const: st,stm32-tamp

Documentation/devicetree/bindings/arm/stm32/stm32.yaml

@@ -161,6 +161,12 @@ properties:
           - const: phytec,phycore-stm32mp157c-som
           - const: st,stm32mp157
 
+      - description: ST STM32MP257 based Boards
+        items:
+          - enum:
+              - st,stm32mp257f-ev1
+          - const: st,stm32mp257
+
 additionalProperties: true
 
 ...

Documentation/devicetree/bindings/clock/nuvoton,ma35d1-clk.yaml

@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/nuvoton,ma35d1-clk.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Nuvoton MA35D1 Clock Controller Module
+
+maintainers:
+  - Chi-Fang Li <[email protected]>
+  - Jacky Huang <[email protected]>
+
+description: |
+  The MA35D1 clock controller generates clocks for the whole chip,
+  including system clocks and all peripheral clocks.
+
+  See also:
+    include/dt-bindings/clock/ma35d1-clk.h
+
+properties:
+  compatible:
+    items:
+      - const: nuvoton,ma35d1-clk
+
+  reg:
+    maxItems: 1
+
+  "#clock-cells":
+    const: 1
+
+  clocks:
+    maxItems: 1
+
+  nuvoton,pll-mode:
+    description:
+      A list of PLL operation mode corresponding to CAPLL, DDRPLL, APLL,
+      EPLL, and VPLL in sequential.
+    maxItems: 5
+    items:
+      enum:
+        - integer
+        - fractional
+        - spread-spectrum
+    $ref: /schemas/types.yaml#/definitions/non-unique-string-array
+
+required:
+  - compatible
+  - reg
+  - "#clock-cells"
+  - clocks
+
+additionalProperties: false
+
+examples:
+  - |
+
+    clock-controller@40460200 {
+        compatible = "nuvoton,ma35d1-clk";
+        reg = <0x40460200 0x100>;
+        #clock-cells = <1>;
+        clocks = <&clk_hxt>;
+    };
+...

Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml

@@ -27,6 +27,8 @@ properties:
       - st,stm32mp135-pinctrl
       - st,stm32mp157-pinctrl
       - st,stm32mp157-z-pinctrl
+      - st,stm32mp257-pinctrl
+      - st,stm32mp257-z-pinctrl
 
   '#address-cells':
     const: 1
@@ -56,7 +58,7 @@ properties:
       Indicates the SOC package used.
       More details in include/dt-bindings/pinctrl/stm32-pinfunc.h
     $ref: /schemas/types.yaml#/definitions/uint32
-    enum: [1, 2, 4, 8]
+    enum: [0x1, 0x2, 0x4, 0x8, 0x100, 0x400, 0x800]
 
 patternProperties:
   '^gpio@[0-9a-f]*$':

Documentation/devicetree/bindings/reset/nuvoton,ma35d1-reset.yaml

@@ -0,0 +1,45 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/nuvoton,ma35d1-reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Nuvoton MA35D1 Reset Controller
+
+maintainers:
+  - Chi-Fang Li <[email protected]>
+  - Jacky Huang <[email protected]>
+
+description:
+  The system reset controller can be used to reset various peripheral
+  controllers in MA35D1 SoC.
+
+properties:
+  compatible:
+    items:
+      - const: nuvoton,ma35d1-reset
+
+  reg:
+    maxItems: 1
+
+  '#reset-cells':
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+  # system reset controller node:
+  - |
+
+    system-management@40460000 {
+        compatible = "nuvoton,ma35d1-reset";
+        reg = <0x40460000 0x200>;
+        #reset-cells = <1>;
+    };
+...
+

Documentation/devicetree/bindings/serial/nuvoton,ma35d1-serial.yaml

@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/serial/nuvoton,ma35d1-serial.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Nuvoton MA35D1 Universal Asynchronous Receiver/Transmitter (UART)
+
+maintainers:
+  - Min-Jen Chen <[email protected]>
+  - Jacky Huang <[email protected]>
+
+allOf:
+  - $ref: serial.yaml
+
+properties:
+  compatible:
+    const: nuvoton,ma35d1-uart
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/clock/nuvoton,ma35d1-clk.h>
+
+    serial@40700000 {
+        compatible = "nuvoton,ma35d1-uart";
+        reg = <0x40700000 0x100>;
+        interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&clk UART0_GATE>;
+    };
+...

Documentation/devicetree/bindings/arm/npcm/nuvoton,gcr.yaml → Documentation/devicetree/bindings/soc/nuvoton/nuvoton,npcm-gcr.yaml

@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
 %YAML 1.2
 ---
-$id: http://devicetree.org/schemas/arm/npcm/nuvoton,gcr.yaml#
+$id: http://devicetree.org/schemas/soc/nuvoton/nuvoton,npcm-gcr.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
 title: Global Control Registers block in Nuvoton SoCs

Documentation/process/maintainer-handbooks.rst

@@ -15,5 +15,6 @@ Contents:
    :numbered:
    :maxdepth: 2
 
-   maintainer-tip
    maintainer-netdev
+   maintainer-soc
+   maintainer-tip