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…/benh/powerpc * 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (152 commits) powerpc: Fix hard CPU IDs detection powerpc/pmac: Update via-pmu to new syscore_ops powerpc/kvm: Fix the build for 32-bit Book 3S (classic) processors powerpc/kvm: Fix kvmppc_core_pending_dec powerpc: Remove last piece of GEMINI powerpc: Fix for Pegasos keyboard and mouse powerpc: Make early memory scan more resilient to out of order nodes powerpc/pseries/iommu: Cleanup ddw naming powerpc/pseries/iommu: Find windows after kexec during boot powerpc/pseries/iommu: Remove ddw property when destroying window powerpc/pseries/iommu: Add additional checks when changing iommu mask powerpc/pseries/iommu: Use correct return type in dupe_ddw_if_already_created powerpc: Remove unused/obsolete CONFIG_XICS misc: Add CARMA DATA-FPGA Programmer support misc: Add CARMA DATA-FPGA Access Driver powerpc: Make IRQ_NOREQUEST last to clear, first to set powerpc: Integrated Flash controller device tree bindings powerpc/85xx: Create dts of each core in CAMP mode for P1020RDB powerpc/85xx: Fix PCIe IDSEL for Px020RDB powerpc/85xx: P2020 DTS: re-organize dts files ...
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,61 @@ | ||
| CAN Device Tree Bindings | ||
| ------------------------ | ||
| 2011 Freescale Semiconductor, Inc. | ||
|
|
||
| fsl,flexcan-v1.0 nodes | ||
| ----------------------- | ||
| In addition to the required compatible-, reg- and interrupt-properties, you can | ||
| also specify which clock source shall be used for the controller. | ||
|
|
||
| CPI Clock- Can Protocol Interface Clock | ||
| This CLK_SRC bit of CTRL(control register) selects the clock source to | ||
| the CAN Protocol Interface(CPI) to be either the peripheral clock | ||
| (driven by the PLL) or the crystal oscillator clock. The selected clock | ||
| is the one fed to the prescaler to generate the Serial Clock (Sclock). | ||
| The PRESDIV field of CTRL(control register) controls a prescaler that | ||
| generates the Serial Clock (Sclock), whose period defines the | ||
| time quantum used to compose the CAN waveform. | ||
|
|
||
| Can Engine Clock Source | ||
| There are two sources for CAN clock | ||
| - Platform Clock It represents the bus clock | ||
| - Oscillator Clock | ||
|
|
||
| Peripheral Clock (PLL) | ||
| -------------- | ||
| | | ||
| --------- ------------- | ||
| | |CPI Clock | Prescaler | Sclock | ||
| | |---------------->| (1.. 256) |------------> | ||
| --------- ------------- | ||
| | | | ||
| -------------- ---------------------CLK_SRC | ||
| Oscillator Clock | ||
|
|
||
| - fsl,flexcan-clock-source : CAN Engine Clock Source.This property selects | ||
| the peripheral clock. PLL clock is fed to the | ||
| prescaler to generate the Serial Clock (Sclock). | ||
| Valid values are "oscillator" and "platform" | ||
| "oscillator": CAN engine clock source is oscillator clock. | ||
| "platform" The CAN engine clock source is the bus clock | ||
| (platform clock). | ||
|
|
||
| - fsl,flexcan-clock-divider : for the reference and system clock, an additional | ||
| clock divider can be specified. | ||
| - clock-frequency: frequency required to calculate the bitrate for FlexCAN. | ||
|
|
||
| Note: | ||
| - v1.0 of flexcan-v1.0 represent the IP block version for P1010 SOC. | ||
| - P1010 does not have oscillator as the Clock Source.So the default | ||
| Clock Source is platform clock. | ||
| Examples: | ||
|
|
||
| can0@1c000 { | ||
| compatible = "fsl,flexcan-v1.0"; | ||
| reg = <0x1c000 0x1000>; | ||
| interrupts = <48 0x2>; | ||
| interrupt-parent = <&mpic>; | ||
| fsl,flexcan-clock-source = "platform"; | ||
| fsl,flexcan-clock-divider = <2>; | ||
| clock-frequency = <fixed by u-boot>; | ||
| }; |
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| Original file line number | Diff line number | Diff line change |
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| Integrated Flash Controller | ||
|
|
||
| Properties: | ||
| - name : Should be ifc | ||
| - compatible : should contain "fsl,ifc". The version of the integrated | ||
| flash controller can be found in the IFC_REV register at | ||
| offset zero. | ||
|
|
||
| - #address-cells : Should be either two or three. The first cell is the | ||
| chipselect number, and the remaining cells are the | ||
| offset into the chipselect. | ||
| - #size-cells : Either one or two, depending on how large each chipselect | ||
| can be. | ||
| - reg : Offset and length of the register set for the device | ||
| - interrupts : IFC has two interrupts. The first one is the "common" | ||
| interrupt(CM_EVTER_STAT), and second is the NAND interrupt | ||
| (NAND_EVTER_STAT). | ||
|
|
||
| - ranges : Each range corresponds to a single chipselect, and covers | ||
| the entire access window as configured. | ||
|
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||
| Child device nodes describe the devices connected to IFC such as NOR (e.g. | ||
| cfi-flash) and NAND (fsl,ifc-nand). There might be board specific devices | ||
| like FPGAs, CPLDs, etc. | ||
|
|
||
| Example: | ||
|
|
||
| ifc@ffe1e000 { | ||
| compatible = "fsl,ifc", "simple-bus"; | ||
| #address-cells = <2>; | ||
| #size-cells = <1>; | ||
| reg = <0x0 0xffe1e000 0 0x2000>; | ||
| interrupts = <16 2 19 2>; | ||
|
|
||
| /* NOR, NAND Flashes and CPLD on board */ | ||
| ranges = <0x0 0x0 0x0 0xee000000 0x02000000 | ||
| 0x1 0x0 0x0 0xffa00000 0x00010000 | ||
| 0x3 0x0 0x0 0xffb00000 0x00020000>; | ||
|
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||
| flash@0,0 { | ||
| #address-cells = <1>; | ||
| #size-cells = <1>; | ||
| compatible = "cfi-flash"; | ||
| reg = <0x0 0x0 0x2000000>; | ||
| bank-width = <2>; | ||
| device-width = <1>; | ||
|
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||
| partition@0 { | ||
| /* 32MB for user data */ | ||
| reg = <0x0 0x02000000>; | ||
| label = "NOR Data"; | ||
| }; | ||
| }; | ||
|
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||
| flash@1,0 { | ||
| #address-cells = <1>; | ||
| #size-cells = <1>; | ||
| compatible = "fsl,ifc-nand"; | ||
| reg = <0x1 0x0 0x10000>; | ||
|
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||
| partition@0 { | ||
| /* This location must not be altered */ | ||
| /* 1MB for u-boot Bootloader Image */ | ||
| reg = <0x0 0x00100000>; | ||
| label = "NAND U-Boot Image"; | ||
| read-only; | ||
| }; | ||
| }; | ||
|
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||
| cpld@3,0 { | ||
| #address-cells = <1>; | ||
| #size-cells = <1>; | ||
| compatible = "fsl,p1010rdb-cpld"; | ||
| reg = <0x3 0x0 0x000001f>; | ||
| }; | ||
| }; |
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Documentation/devicetree/bindings/powerpc/fsl/mpic-timer.txt
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| * Freescale MPIC timers | ||
|
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||
| Required properties: | ||
| - compatible: "fsl,mpic-global-timer" | ||
|
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| - reg : Contains two regions. The first is the main timer register bank | ||
| (GTCCRxx, GTBCRxx, GTVPRxx, GTDRxx). The second is the timer control | ||
| register (TCRx) for the group. | ||
|
|
||
| - fsl,available-ranges: use <start count> style section to define which | ||
| timer interrupts can be used. This property is optional; without this, | ||
| all timers within the group can be used. | ||
|
|
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| - interrupts: one interrupt per timer in the group, in order, starting | ||
| with timer zero. If timer-available-ranges is present, only the | ||
| interrupts that correspond to available timers shall be present. | ||
|
|
||
| Example: | ||
| /* Note that this requires #interrupt-cells to be 4 */ | ||
| timer0: timer@41100 { | ||
| compatible = "fsl,mpic-global-timer"; | ||
| reg = <0x41100 0x100 0x41300 4>; | ||
|
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||
| /* Another AMP partition is using timers 0 and 1 */ | ||
| fsl,available-ranges = <2 2>; | ||
|
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| interrupts = <2 0 3 0 | ||
| 3 0 3 0>; | ||
| }; | ||
|
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| timer1: timer@42100 { | ||
| compatible = "fsl,mpic-global-timer"; | ||
| reg = <0x42100 0x100 0x42300 4>; | ||
| interrupts = <4 0 3 0 | ||
| 5 0 3 0 | ||
| 6 0 3 0 | ||
| 7 0 3 0>; | ||
| }; |
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