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Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
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Cross-merge networking fixes after downstream PR.

No conflicts, or adjacent changes.

Signed-off-by: Jakub Kicinski <[email protected]>
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kuba-moo committed Mar 29, 2024
2 parents 2a702c2 + 50108c3 commit 5e47fbe
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6 changes: 4 additions & 2 deletions .mailmap
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Expand Up @@ -340,7 +340,8 @@ Lee Jones <[email protected]> <[email protected]>
Lee Jones <[email protected]> <[email protected]>
Lee Jones <[email protected]> <[email protected]>
Lee Jones <[email protected]> <[email protected]>
Leonard Crestez <[email protected]> Leonard Crestez <[email protected]>
Leonard Crestez <[email protected]> <[email protected]>
Leonard Crestez <[email protected]> <[email protected]>
Leonardo Bras <[email protected]> <[email protected]>
Leonard Göhrs <[email protected]>
Leonid I Ananiev <[email protected]>
Expand Down Expand Up @@ -497,7 +498,8 @@ Prasad Sodagudi <[email protected]> <[email protected]>
Punit Agrawal <[email protected]> <[email protected]>
Qais Yousef <[email protected]> <[email protected]>
Qais Yousef <[email protected]> <[email protected]>
Quentin Monnet <[email protected]> <[email protected]>
Quentin Monnet <[email protected]> <[email protected]>
Quentin Monnet <[email protected]> <[email protected]>
Quentin Perret <[email protected]> <[email protected]>
Rafael J. Wysocki <[email protected]> <[email protected]>
Rajeev Nandan <[email protected]> <[email protected]>
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16 changes: 5 additions & 11 deletions Documentation/arch/riscv/vm-layout.rst
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Expand Up @@ -144,14 +144,8 @@ passing 0 into the hint address parameter of mmap. On CPUs with an address space
smaller than sv48, the CPU maximum supported address space will be the default.

Software can "opt-in" to receiving VAs from another VA space by providing
a hint address to mmap. A hint address passed to mmap will cause the largest
address space that fits entirely into the hint to be used, unless there is no
space left in the address space. If there is no space available in the requested
address space, an address in the next smallest available address space will be
returned.

For example, in order to obtain 48-bit VA space, a hint address greater than
:code:`1 << 47` must be provided. Note that this is 47 due to sv48 userspace
ending at :code:`1 << 47` and the addresses beyond this are reserved for the
kernel. Similarly, to obtain 57-bit VA space addresses, a hint address greater
than or equal to :code:`1 << 56` must be provided.
a hint address to mmap. When a hint address is passed to mmap, the returned
address will never use more bits than the hint address. For example, if a hint
address of `1 << 40` is passed to mmap, a valid returned address will never use
bits 41 through 63. If no mappable addresses are available in that range, mmap
will return `MAP_FAILED`.
8 changes: 4 additions & 4 deletions Documentation/arch/x86/resctrl.rst
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Expand Up @@ -45,7 +45,7 @@ mount options are:
Enable code/data prioritization in L2 cache allocations.
"mba_MBps":
Enable the MBA Software Controller(mba_sc) to specify MBA
bandwidth in MBps
bandwidth in MiBps
"debug":
Make debug files accessible. Available debug files are annotated with
"Available only with debug option".
Expand Down Expand Up @@ -526,7 +526,7 @@ threads start using more cores in an rdtgroup, the actual bandwidth may
increase or vary although user specified bandwidth percentage is same.

In order to mitigate this and make the interface more user friendly,
resctrl added support for specifying the bandwidth in MBps as well. The
resctrl added support for specifying the bandwidth in MiBps as well. The
kernel underneath would use a software feedback mechanism or a "Software
Controller(mba_sc)" which reads the actual bandwidth using MBM counters
and adjust the memory bandwidth percentages to ensure::
Expand Down Expand Up @@ -573,13 +573,13 @@ Memory b/w domain is L3 cache.

MB:<cache_id0>=bandwidth0;<cache_id1>=bandwidth1;...

Memory bandwidth Allocation specified in MBps
Memory bandwidth Allocation specified in MiBps
---------------------------------------------

Memory bandwidth domain is L3 cache.
::

MB:<cache_id0>=bw_MBps0;<cache_id1>=bw_MBps1;...
MB:<cache_id0>=bw_MiBps0;<cache_id1>=bw_MiBps1;...

Slow Memory Bandwidth Allocation (SMBA)
---------------------------------------
Expand Down
2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
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Expand Up @@ -270,7 +270,7 @@ examples:
port {
ov7251_ep: endpoint {
data-lanes = <0 1>;
data-lanes = <0>;
link-frequencies = /bits/ 64 <240000000 319200000>;
remote-endpoint = <&csiphy3_ep>;
};
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49 changes: 43 additions & 6 deletions Documentation/devicetree/bindings/i2c/st,nomadik-i2c.yaml
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Expand Up @@ -14,31 +14,30 @@ description: The Nomadik I2C host controller began its life in the ST
maintainers:
- Linus Walleij <[email protected]>

allOf:
- $ref: /schemas/i2c/i2c-controller.yaml#

# Need a custom select here or 'arm,primecell' will match on lots of nodes
select:
properties:
compatible:
contains:
enum:
- st,nomadik-i2c
- mobileye,eyeq5-i2c
required:
- compatible

properties:
compatible:
oneOf:
# The variant found in STn8815
- items:
- const: st,nomadik-i2c
- const: arm,primecell
# The variant found in DB8500
- items:
- const: stericsson,db8500-i2c
- const: st,nomadik-i2c
- const: arm,primecell
- items:
- const: mobileye,eyeq5-i2c
- const: arm,primecell

reg:
maxItems: 1
Expand All @@ -55,7 +54,7 @@ properties:
- items:
- const: mclk
- const: apb_pclk
# Clock name in DB8500
# Clock name in DB8500 or EyeQ5
- items:
- const: i2cclk
- const: apb_pclk
Expand All @@ -70,6 +69,16 @@ properties:
minimum: 1
maximum: 400000

mobileye,olb:
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
- items:
- description: Phandle to OLB system controller node.
- description: Platform-wide controller ID (integer starting from zero).
description:
The phandle pointing to OLB system controller node, with the I2C
controller index.

required:
- compatible
- reg
Expand All @@ -79,6 +88,20 @@ required:

unevaluatedProperties: false

allOf:
- $ref: /schemas/i2c/i2c-controller.yaml#
- if:
properties:
compatible:
contains:
const: mobileye,eyeq5-i2c
then:
required:
- mobileye,olb
else:
properties:
mobileye,olb: false

examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
Expand Down Expand Up @@ -111,5 +134,19 @@ examples:
clocks = <&i2c0clk>, <&pclki2c0>;
clock-names = "mclk", "apb_pclk";
};
- |
#include <dt-bindings/interrupt-controller/mips-gic.h>
i2c@300000 {
compatible = "mobileye,eyeq5-i2c", "arm,primecell";
reg = <0x300000 0x1000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 1 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <400000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&i2c_ser_clk>, <&i2c_clk>;
clock-names = "i2cclk", "apb_pclk";
mobileye,olb = <&olb 0>;
};
...
75 changes: 75 additions & 0 deletions Documentation/devicetree/bindings/mtd/partitions/linux,ubi.yaml
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@@ -0,0 +1,75 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/partitions/linux,ubi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Unsorted Block Images

description: |
UBI ("Unsorted Block Images") is a volume management system for raw
flash devices which manages multiple logical volumes on a single
physical flash device and spreads the I/O load (i.e wear-leveling)
across the whole flash chip.
maintainers:
- Daniel Golle <[email protected]>

allOf:
- $ref: partition.yaml#

properties:
compatible:
const: linux,ubi

volumes:
type: object
description: UBI Volumes

patternProperties:
"^ubi-volume-.*$":
$ref: /schemas/mtd/partitions/ubi-volume.yaml#

unevaluatedProperties: false

required:
- compatible

unevaluatedProperties: false

examples:
- |
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
reg = <0x0 0x100000>;
label = "bootloader";
read-only;
};
partition@100000 {
reg = <0x100000 0x1ff00000>;
label = "ubi";
compatible = "linux,ubi";
volumes {
ubi-volume-caldata {
volid = <2>;
volname = "rf";
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
eeprom@0 {
reg = <0x0 0x1000>;
};
};
};
};
};
};
40 changes: 40 additions & 0 deletions Documentation/devicetree/bindings/mtd/partitions/ubi-volume.yaml
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@@ -0,0 +1,40 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/partitions/ubi-volume.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: UBI volume

description: |
This binding describes a single UBI volume. Volumes can be matches either
by their ID or their name, or both.
maintainers:
- Daniel Golle <[email protected]>

properties:
volid:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Match UBI volume ID

volname:
$ref: /schemas/types.yaml#/definitions/string
description:
Match UBI volume ID

nvmem-layout:
$ref: /schemas/nvmem/layouts/nvmem-layout.yaml#
description:
This container may reference an NVMEM layout parser.

anyOf:
- required:
- volid

- required:
- volname

# This is a generic file other binding inherit from and extend
additionalProperties: true
6 changes: 5 additions & 1 deletion Documentation/devicetree/bindings/riscv/cpus.yaml
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Expand Up @@ -110,7 +110,11 @@ properties:
const: 1

compatible:
const: riscv,cpu-intc
oneOf:
- items:
- const: andestech,cpu-intc
- const: riscv,cpu-intc
- const: riscv,cpu-intc

interrupt-controller: true

Expand Down
7 changes: 7 additions & 0 deletions Documentation/devicetree/bindings/riscv/extensions.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -477,5 +477,12 @@ properties:
latency, as ratified in commit 56ed795 ("Update
riscv-crypto-spec-vector.adoc") of riscv-crypto.

- const: xandespmu
description:
The Andes Technology performance monitor extension for counter overflow
and privilege mode filtering. For more details, see Counter Related
Registers in the AX45MP datasheet.
https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf

additionalProperties: true
...
31 changes: 0 additions & 31 deletions Documentation/devicetree/bindings/rtc/abracon,abx80x.txt

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