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Merge tag 'tty-3.10-rc1' of git://git.kernel.org/pub/scm/linux/kernel…
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…/git/gregkh/tty

Pull tty/serial driver update from Greg Kroah-Hartman:
 "Here's the big tty/serial driver merge request for 3.10-rc1

  Once again, Jiri has a number of TTY driver fixes and cleanups, and
  Peter Hurley came through with a bunch of ldisc fixes that resolve a
  number of reported issues.  There are some other serial driver
  cleanups as well.

  All of these have been in the linux-next tree for a while"

* tag 'tty-3.10-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty: (117 commits)
  tty/serial/sirf: fix MODULE_DEVICE_TABLE
  serial: mxs: drop superfluous {get|put}_device
  serial: mxs: fix buffer overflow
  ARM: PL011: add support for extended FIFO-size of PL011-r1p5
  serial_core.c: add put_device() after device_find_child()
  tty: Fix unsafe bit ops in tty_throttle_safe/unthrottle_safe
  serial: sccnxp: Replace pdata.init/exit with regulator API
  serial: sccnxp: Do not override device name
  TTY: pty, fix compilation warning
  TTY: rocket, fix compilation warning
  TTY: ircomm: fix DTR being raised on hang up
  TTY: synclinkmp: fix DTR being raised on hang up
  TTY: synclink_gt: fix DTR being raised on hang up
  TTY: synclink: fix DTR being raised on hang up
  serial: 8250_dw: Fix the stub for dw8250_probe_acpi()
  serial: 8250_dw: Convert to devm_ioremap()
  serial: 8250_dw: Set port capabilities based on CPR register
  serial: 8250_dw: Let ACPI code extract the DMA client info
  serial: 8250_dw: Support clk framework also with ACPI
  serial: 8250_dw: Enable runtime PM
  ...
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@torvalds
torvalds committed Apr 29, 2013
2 parents fdc719b + 45efcb2 commit 507ffe4
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4 changes: 4 additions & 0 deletions Documentation/devicetree/bindings/tty/serial/of-serial.txt
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Expand Up @@ -33,6 +33,10 @@ Optional properties:
RTAS and should not be registered.
- no-loopback-test: set to indicate that the port does not implements loopback
test mode
- fifo-size: the fifo size of the UART.
- auto-flow-control: one way to enable automatic flow control support. The
driver is allowed to detect support for the capability even without this
property.

Example:

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5 changes: 5 additions & 0 deletions arch/arm/mach-s3c24xx/clock-s3c2440.c
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Expand Up @@ -123,6 +123,11 @@ static struct clk s3c2440_clk_ac97 = {
.ctrlbit = S3C2440_CLKCON_AC97,
};

#define S3C24XX_VA_UART0 (S3C_VA_UART)
#define S3C24XX_VA_UART1 (S3C_VA_UART + 0x4000 )
#define S3C24XX_VA_UART2 (S3C_VA_UART + 0x8000 )
#define S3C24XX_VA_UART3 (S3C_VA_UART + 0xC000 )

static unsigned long s3c2440_fclk_n_getrate(struct clk *clk)
{
unsigned long ucon0, ucon1, ucon2, divisor;
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5 changes: 5 additions & 0 deletions arch/arm/mach-s3c24xx/common.c
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Expand Up @@ -239,6 +239,11 @@ void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)

/* Serial port registrations */

#define S3C2410_PA_UART0 (S3C24XX_PA_UART)
#define S3C2410_PA_UART1 (S3C24XX_PA_UART + 0x4000 )
#define S3C2410_PA_UART2 (S3C24XX_PA_UART + 0x8000 )
#define S3C2443_PA_UART3 (S3C24XX_PA_UART + 0xC000 )

static struct resource s3c2410_uart0_resource[] = {
[0] = DEFINE_RES_MEM(S3C2410_PA_UART0, SZ_16K),
[1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX0, \
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282 changes: 1 addition & 281 deletions arch/arm/plat-samsung/include/plat/regs-serial.h
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@@ -1,281 +1 @@
/* arch/arm/plat-samsung/include/plat/regs-serial.h
*
* From linux/include/asm-arm/hardware/serial_s3c2410.h
*
* Internal header file for Samsung S3C2410 serial ports (UART0-2)
*
* Copyright (C) 2002 Shane Nay ([email protected])
*
* Additional defines, Copyright 2003 Simtec Electronics ([email protected])
*
* Adapted from:
*
* Internal header file for MX1ADS serial ports (UART1 & 2)
*
* Copyright (C) 2002 Shane Nay ([email protected])
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/

#ifndef __ASM_ARM_REGS_SERIAL_H
#define __ASM_ARM_REGS_SERIAL_H

#define S3C24XX_VA_UART0 (S3C_VA_UART)
#define S3C24XX_VA_UART1 (S3C_VA_UART + 0x4000 )
#define S3C24XX_VA_UART2 (S3C_VA_UART + 0x8000 )
#define S3C24XX_VA_UART3 (S3C_VA_UART + 0xC000 )

#define S3C2410_PA_UART0 (S3C24XX_PA_UART)
#define S3C2410_PA_UART1 (S3C24XX_PA_UART + 0x4000 )
#define S3C2410_PA_UART2 (S3C24XX_PA_UART + 0x8000 )
#define S3C2443_PA_UART3 (S3C24XX_PA_UART + 0xC000 )

#define S3C2410_URXH (0x24)
#define S3C2410_UTXH (0x20)
#define S3C2410_ULCON (0x00)
#define S3C2410_UCON (0x04)
#define S3C2410_UFCON (0x08)
#define S3C2410_UMCON (0x0C)
#define S3C2410_UBRDIV (0x28)
#define S3C2410_UTRSTAT (0x10)
#define S3C2410_UERSTAT (0x14)
#define S3C2410_UFSTAT (0x18)
#define S3C2410_UMSTAT (0x1C)

#define S3C2410_LCON_CFGMASK ((0xF<<3)|(0x3))

#define S3C2410_LCON_CS5 (0x0)
#define S3C2410_LCON_CS6 (0x1)
#define S3C2410_LCON_CS7 (0x2)
#define S3C2410_LCON_CS8 (0x3)
#define S3C2410_LCON_CSMASK (0x3)

#define S3C2410_LCON_PNONE (0x0)
#define S3C2410_LCON_PEVEN (0x5 << 3)
#define S3C2410_LCON_PODD (0x4 << 3)
#define S3C2410_LCON_PMASK (0x7 << 3)

#define S3C2410_LCON_STOPB (1<<2)
#define S3C2410_LCON_IRM (1<<6)

#define S3C2440_UCON_CLKMASK (3<<10)
#define S3C2440_UCON_CLKSHIFT (10)
#define S3C2440_UCON_PCLK (0<<10)
#define S3C2440_UCON_UCLK (1<<10)
#define S3C2440_UCON_PCLK2 (2<<10)
#define S3C2440_UCON_FCLK (3<<10)
#define S3C2443_UCON_EPLL (3<<10)

#define S3C6400_UCON_CLKMASK (3<<10)
#define S3C6400_UCON_CLKSHIFT (10)
#define S3C6400_UCON_PCLK (0<<10)
#define S3C6400_UCON_PCLK2 (2<<10)
#define S3C6400_UCON_UCLK0 (1<<10)
#define S3C6400_UCON_UCLK1 (3<<10)

#define S3C2440_UCON2_FCLK_EN (1<<15)
#define S3C2440_UCON0_DIVMASK (15 << 12)
#define S3C2440_UCON1_DIVMASK (15 << 12)
#define S3C2440_UCON2_DIVMASK (7 << 12)
#define S3C2440_UCON_DIVSHIFT (12)

#define S3C2412_UCON_CLKMASK (3<<10)
#define S3C2412_UCON_CLKSHIFT (10)
#define S3C2412_UCON_UCLK (1<<10)
#define S3C2412_UCON_USYSCLK (3<<10)
#define S3C2412_UCON_PCLK (0<<10)
#define S3C2412_UCON_PCLK2 (2<<10)

#define S3C2410_UCON_CLKMASK (1 << 10)
#define S3C2410_UCON_CLKSHIFT (10)
#define S3C2410_UCON_UCLK (1<<10)
#define S3C2410_UCON_SBREAK (1<<4)

#define S3C2410_UCON_TXILEVEL (1<<9)
#define S3C2410_UCON_RXILEVEL (1<<8)
#define S3C2410_UCON_TXIRQMODE (1<<2)
#define S3C2410_UCON_RXIRQMODE (1<<0)
#define S3C2410_UCON_RXFIFO_TOI (1<<7)
#define S3C2443_UCON_RXERR_IRQEN (1<<6)
#define S3C2443_UCON_LOOPBACK (1<<5)

#define S3C2410_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
S3C2410_UCON_RXILEVEL | \
S3C2410_UCON_TXIRQMODE | \
S3C2410_UCON_RXIRQMODE | \
S3C2410_UCON_RXFIFO_TOI)

#define S3C2410_UFCON_FIFOMODE (1<<0)
#define S3C2410_UFCON_TXTRIG0 (0<<6)
#define S3C2410_UFCON_RXTRIG8 (1<<4)
#define S3C2410_UFCON_RXTRIG12 (2<<4)

/* S3C2440 FIFO trigger levels */
#define S3C2440_UFCON_RXTRIG1 (0<<4)
#define S3C2440_UFCON_RXTRIG8 (1<<4)
#define S3C2440_UFCON_RXTRIG16 (2<<4)
#define S3C2440_UFCON_RXTRIG32 (3<<4)

#define S3C2440_UFCON_TXTRIG0 (0<<6)
#define S3C2440_UFCON_TXTRIG16 (1<<6)
#define S3C2440_UFCON_TXTRIG32 (2<<6)
#define S3C2440_UFCON_TXTRIG48 (3<<6)

#define S3C2410_UFCON_RESETBOTH (3<<1)
#define S3C2410_UFCON_RESETTX (1<<2)
#define S3C2410_UFCON_RESETRX (1<<1)

#define S3C2410_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
S3C2410_UFCON_TXTRIG0 | \
S3C2410_UFCON_RXTRIG8 )

#define S3C2410_UMCOM_AFC (1<<4)
#define S3C2410_UMCOM_RTS_LOW (1<<0)

#define S3C2412_UMCON_AFC_63 (0<<5) /* same as s3c2443 */
#define S3C2412_UMCON_AFC_56 (1<<5)
#define S3C2412_UMCON_AFC_48 (2<<5)
#define S3C2412_UMCON_AFC_40 (3<<5)
#define S3C2412_UMCON_AFC_32 (4<<5)
#define S3C2412_UMCON_AFC_24 (5<<5)
#define S3C2412_UMCON_AFC_16 (6<<5)
#define S3C2412_UMCON_AFC_8 (7<<5)

#define S3C2410_UFSTAT_TXFULL (1<<9)
#define S3C2410_UFSTAT_RXFULL (1<<8)
#define S3C2410_UFSTAT_TXMASK (15<<4)
#define S3C2410_UFSTAT_TXSHIFT (4)
#define S3C2410_UFSTAT_RXMASK (15<<0)
#define S3C2410_UFSTAT_RXSHIFT (0)

/* UFSTAT S3C2443 same as S3C2440 */
#define S3C2440_UFSTAT_TXFULL (1<<14)
#define S3C2440_UFSTAT_RXFULL (1<<6)
#define S3C2440_UFSTAT_TXSHIFT (8)
#define S3C2440_UFSTAT_RXSHIFT (0)
#define S3C2440_UFSTAT_TXMASK (63<<8)
#define S3C2440_UFSTAT_RXMASK (63)

#define S3C2410_UTRSTAT_TXE (1<<2)
#define S3C2410_UTRSTAT_TXFE (1<<1)
#define S3C2410_UTRSTAT_RXDR (1<<0)

#define S3C2410_UERSTAT_OVERRUN (1<<0)
#define S3C2410_UERSTAT_FRAME (1<<2)
#define S3C2410_UERSTAT_BREAK (1<<3)
#define S3C2443_UERSTAT_PARITY (1<<1)

#define S3C2410_UERSTAT_ANY (S3C2410_UERSTAT_OVERRUN | \
S3C2410_UERSTAT_FRAME | \
S3C2410_UERSTAT_BREAK)

#define S3C2410_UMSTAT_CTS (1<<0)
#define S3C2410_UMSTAT_DeltaCTS (1<<2)

#define S3C2443_DIVSLOT (0x2C)

/* S3C64XX interrupt registers. */
#define S3C64XX_UINTP 0x30
#define S3C64XX_UINTSP 0x34
#define S3C64XX_UINTM 0x38

#define S3C64XX_UINTM_RXD (0)
#define S3C64XX_UINTM_TXD (2)
#define S3C64XX_UINTM_RXD_MSK (1 << S3C64XX_UINTM_RXD)
#define S3C64XX_UINTM_TXD_MSK (1 << S3C64XX_UINTM_TXD)

/* Following are specific to S5PV210 */
#define S5PV210_UCON_CLKMASK (1<<10)
#define S5PV210_UCON_CLKSHIFT (10)
#define S5PV210_UCON_PCLK (0<<10)
#define S5PV210_UCON_UCLK (1<<10)

#define S5PV210_UFCON_TXTRIG0 (0<<8)
#define S5PV210_UFCON_TXTRIG4 (1<<8)
#define S5PV210_UFCON_TXTRIG8 (2<<8)
#define S5PV210_UFCON_TXTRIG16 (3<<8)
#define S5PV210_UFCON_TXTRIG32 (4<<8)
#define S5PV210_UFCON_TXTRIG64 (5<<8)
#define S5PV210_UFCON_TXTRIG128 (6<<8)
#define S5PV210_UFCON_TXTRIG256 (7<<8)

#define S5PV210_UFCON_RXTRIG1 (0<<4)
#define S5PV210_UFCON_RXTRIG4 (1<<4)
#define S5PV210_UFCON_RXTRIG8 (2<<4)
#define S5PV210_UFCON_RXTRIG16 (3<<4)
#define S5PV210_UFCON_RXTRIG32 (4<<4)
#define S5PV210_UFCON_RXTRIG64 (5<<4)
#define S5PV210_UFCON_RXTRIG128 (6<<4)
#define S5PV210_UFCON_RXTRIG256 (7<<4)

#define S5PV210_UFSTAT_TXFULL (1<<24)
#define S5PV210_UFSTAT_RXFULL (1<<8)
#define S5PV210_UFSTAT_TXMASK (255<<16)
#define S5PV210_UFSTAT_TXSHIFT (16)
#define S5PV210_UFSTAT_RXMASK (255<<0)
#define S5PV210_UFSTAT_RXSHIFT (0)

#define S3C2410_UCON_CLKSEL0 (1 << 0)
#define S3C2410_UCON_CLKSEL1 (1 << 1)
#define S3C2410_UCON_CLKSEL2 (1 << 2)
#define S3C2410_UCON_CLKSEL3 (1 << 3)

/* Default values for s5pv210 UCON and UFCON uart registers */
#define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
S3C2410_UCON_RXILEVEL | \
S3C2410_UCON_TXIRQMODE | \
S3C2410_UCON_RXIRQMODE | \
S3C2410_UCON_RXFIFO_TOI | \
S3C2443_UCON_RXERR_IRQEN)

#define S5PV210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
S5PV210_UFCON_TXTRIG4 | \
S5PV210_UFCON_RXTRIG4)

#ifndef __ASSEMBLY__

/* configuration structure for per-machine configurations for the
* serial port
*
* the pointer is setup by the machine specific initialisation from the
* arch/arm/mach-s3c2410/ directory.
*/

struct s3c2410_uartcfg {
unsigned char hwport; /* hardware port number */
unsigned char unused;
unsigned short flags;
upf_t uart_flags; /* default uart flags */
unsigned int clk_sel;

unsigned int has_fracval;

unsigned long ucon; /* value of ucon for port */
unsigned long ulcon; /* value of ulcon for port */
unsigned long ufcon; /* value of ufcon for port */
};

/* s3c24xx_uart_devs
*
* this is exported from the core as we cannot use driver_register(),
* or platform_add_device() before the console_initcall()
*/

extern struct platform_device *s3c24xx_uart_devs[4];

#endif /* __ASSEMBLY__ */

#endif /* __ASM_ARM_REGS_SERIAL_H */

#include <linux/serial_s3c.h>
16 changes: 3 additions & 13 deletions arch/ia64/hp/sim/simserial.c
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Original file line number Diff line number Diff line change
Expand Up @@ -142,8 +142,7 @@ static void transmit_chars(struct tty_struct *tty, struct serial_state *info,
goto out;
}

if (info->xmit.head == info->xmit.tail || tty->stopped ||
tty->hw_stopped) {
if (info->xmit.head == info->xmit.tail || tty->stopped) {
#ifdef SIMSERIAL_DEBUG
printk("transmit_chars: head=%d, tail=%d, stopped=%d\n",
info->xmit.head, info->xmit.tail, tty->stopped);
Expand Down Expand Up @@ -181,7 +180,7 @@ static void rs_flush_chars(struct tty_struct *tty)
struct serial_state *info = tty->driver_data;

if (info->xmit.head == info->xmit.tail || tty->stopped ||
tty->hw_stopped || !info->xmit.buf)
!info->xmit.buf)
return;

transmit_chars(tty, info, NULL);
Expand Down Expand Up @@ -217,7 +216,7 @@ static int rs_write(struct tty_struct * tty,
* Hey, we transmit directly from here in our case
*/
if (CIRC_CNT(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE) &&
!tty->stopped && !tty->hw_stopped)
!tty->stopped)
transmit_chars(tty, info, NULL);

return ret;
Expand Down Expand Up @@ -325,14 +324,6 @@ static int rs_ioctl(struct tty_struct *tty, unsigned int cmd, unsigned long arg)

#define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))

static void rs_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
{
/* Handle turning off CRTSCTS */
if ((old_termios->c_cflag & CRTSCTS) &&
!(tty->termios.c_cflag & CRTSCTS)) {
tty->hw_stopped = 0;
}
}
/*
* This routine will shutdown a serial port; interrupts are disabled, and
* DTR is dropped if the hangup on close termio flag is on.
Expand Down Expand Up @@ -481,7 +472,6 @@ static const struct tty_operations hp_ops = {
.throttle = rs_throttle,
.unthrottle = rs_unthrottle,
.send_xchar = rs_send_xchar,
.set_termios = rs_set_termios,
.hangup = rs_hangup,
.proc_fops = &rs_proc_fops,
};
Expand Down
6 changes: 1 addition & 5 deletions arch/um/drivers/chan_kern.c
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Original file line number Diff line number Diff line change
Expand Up @@ -568,11 +568,7 @@ void chan_interrupt(struct line *line, int irq)
reactivate_fd(chan->fd, irq);
if (err == -EIO) {
if (chan->primary) {
struct tty_struct *tty = tty_port_tty_get(&line->port);
if (tty != NULL) {
tty_hangup(tty);
tty_kref_put(tty);
}
tty_port_tty_hangup(&line->port, false);
if (line->chan_out != chan)
close_one_chan(line->chan_out, 1);
}
Expand Down
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