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Merge tag 'tegra-for-5.14-dt-bindings' of git://git.kernel.org/pub/sc…
…m/linux/kernel/git/tegra/linux into arm/dt dt-bindings: Changes for v5.14-rc1 This contains a conversion of the Tegra clock and reset controller device tree bindings to the new json-schema format and adds the core power domain to the PMC device tree bindings. * tag 'tegra-for-5.14-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: dt-bindings: soc: tegra-pmc: Document core power domain dt-bindings: clock: tegra: Convert to schema Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Olof Johansson <[email protected]>
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Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt
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Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt
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Documentation/devicetree/bindings/clock/nvidia,tegra124-car.yaml
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# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause) | ||
%YAML 1.2 | ||
--- | ||
$id: http://devicetree.org/schemas/clock/nvidia,tegra124-car.yaml# | ||
$schema: http://devicetree.org/meta-schemas/core.yaml# | ||
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title: NVIDIA Tegra Clock and Reset Controller | ||
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maintainers: | ||
- Jon Hunter <[email protected]> | ||
- Thierry Reding <[email protected]> | ||
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description: | | ||
The Clock and Reset (CAR) is the HW module responsible for muxing and gating | ||
Tegra's clocks, and setting their rates. It comprises CLKGEN and RSTGEN units. | ||
CLKGEN provides the registers to program the PLLs. It controls most of | ||
the clock source programming and most of the clock dividers. | ||
CLKGEN input signals include the external clock for the reference frequency | ||
(12 MHz, 26 MHz) and the external clock for the Real Time Clock (32.768 KHz). | ||
Outputs from CLKGEN are inputs clock of the h/w blocks in the Tegra system. | ||
RSTGEN provides the registers needed to control resetting of each block in | ||
the Tegra system. | ||
properties: | ||
compatible: | ||
const: nvidia,tegra124-car | ||
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reg: | ||
maxItems: 1 | ||
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'#clock-cells': | ||
const: 1 | ||
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"#reset-cells": | ||
const: 1 | ||
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nvidia,external-memory-controller: | ||
$ref: /schemas/types.yaml#/definitions/phandle | ||
description: | ||
phandle of the external memory controller node | ||
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patternProperties: | ||
"^emc-timings-[0-9]+$": | ||
type: object | ||
properties: | ||
nvidia,ram-code: | ||
$ref: /schemas/types.yaml#/definitions/uint32 | ||
description: | ||
value of the RAM_CODE field in the PMC_STRAPPING_OPT_A register that | ||
this timing set is used for | ||
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patternProperties: | ||
"^timing-[0-9]+$": | ||
type: object | ||
properties: | ||
clock-frequency: | ||
description: | ||
external memory clock rate in Hz | ||
minimum: 1000000 | ||
maximum: 1000000000 | ||
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nvidia,parent-clock-frequency: | ||
$ref: /schemas/types.yaml#/definitions/uint32 | ||
description: | ||
rate of parent clock in Hz | ||
minimum: 1000000 | ||
maximum: 1000000000 | ||
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clocks: | ||
items: | ||
- description: parent clock of EMC | ||
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clock-names: | ||
items: | ||
- const: emc-parent | ||
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required: | ||
- clock-frequency | ||
- nvidia,parent-clock-frequency | ||
- clocks | ||
- clock-names | ||
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additionalProperties: false | ||
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additionalProperties: false | ||
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required: | ||
- compatible | ||
- reg | ||
- '#clock-cells' | ||
- "#reset-cells" | ||
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additionalProperties: false | ||
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examples: | ||
- | | ||
#include <dt-bindings/clock/tegra124-car.h> | ||
car: clock-controller@60006000 { | ||
compatible = "nvidia,tegra124-car"; | ||
reg = <0x60006000 0x1000>; | ||
#clock-cells = <1>; | ||
#reset-cells = <1>; | ||
}; | ||
usb-controller@c5004000 { | ||
compatible = "nvidia,tegra20-ehci"; | ||
reg = <0xc5004000 0x4000>; | ||
clocks = <&car TEGRA124_CLK_USB2>; | ||
resets = <&car TEGRA124_CLK_USB2>; | ||
}; |
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