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Merge branch 'late/clksrc' into late/cleanup
There is no reason to keep the clksrc cleanups separate from the other cleanups, and this resolves some merge conflicts. Conflicts: arch/arm/mach-spear/spear13xx.c drivers/irqchip/Makefile
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Frequently asked questions about the sunxi clock system | ||
======================================================= | ||
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This document contains useful bits of information that people tend to ask | ||
about the sunxi clock system, as well as accompanying ASCII art when adequate. | ||
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Q: Why is the main 24MHz oscillator gatable? Wouldn't that break the | ||
system? | ||
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A: The 24MHz oscillator allows gating to save power. Indeed, if gated | ||
carelessly the system would stop functioning, but with the right | ||
steps, one can gate it and keep the system running. Consider this | ||
simplified suspend example: | ||
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While the system is operational, you would see something like | ||
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24MHz 32kHz | ||
| | ||
PLL1 | ||
\ | ||
\_ CPU Mux | ||
| | ||
[CPU] | ||
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When you are about to suspend, you switch the CPU Mux to the 32kHz | ||
oscillator: | ||
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24Mhz 32kHz | ||
| | | ||
PLL1 | | ||
/ | ||
CPU Mux _/ | ||
| | ||
[CPU] | ||
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Finally you can gate the main oscillator | ||
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32kHz | ||
| | ||
| | ||
/ | ||
CPU Mux _/ | ||
| | ||
[CPU] | ||
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Q: Were can I learn more about the sunxi clocks? | ||
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A: The linux-sunxi wiki contains a page documenting the clock registers, | ||
you can find it at | ||
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http://linux-sunxi.org/A10/CCM | ||
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The authoritative source for information at this time is the ccmu driver | ||
released by Allwinner, you can find it at | ||
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https://github.com/linux-sunxi/linux-sunxi/tree/sunxi-3.0/arch/arm/mach-sun4i/clock/ccmu |
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67 changes: 66 additions & 1 deletion
67
Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt
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NVIDIA Tegra Power Management Controller (PMC) | ||
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Properties: | ||
The PMC block interacts with an external Power Management Unit. The PMC | ||
mostly controls the entry and exit of the system from different sleep | ||
modes. It provides power-gating controllers for SoC and CPU power-islands. | ||
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Required properties: | ||
- name : Should be pmc | ||
- compatible : Should contain "nvidia,tegra<chip>-pmc". | ||
- reg : Offset and length of the register set for the device | ||
- clocks : Must contain an entry for each entry in clock-names. | ||
- clock-names : Must include the following entries: | ||
"pclk" (The Tegra clock of that name), | ||
"clk32k_in" (The 32KHz clock input to Tegra). | ||
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Optional properties: | ||
- nvidia,invert-interrupt : If present, inverts the PMU interrupt signal. | ||
The PMU is an external Power Management Unit, whose interrupt output | ||
signal is fed into the PMC. This signal is optionally inverted, and then | ||
fed into the ARM GIC. The PMC is not involved in the detection or | ||
handling of this interrupt signal, merely its inversion. | ||
- nvidia,suspend-mode : The suspend mode that the platform should use. | ||
Valid values are 0, 1 and 2: | ||
0 (LP0): CPU + Core voltage off and DRAM in self-refresh | ||
1 (LP1): CPU voltage off and DRAM in self-refresh | ||
2 (LP2): CPU voltage off | ||
- nvidia,core-power-req-active-high : Boolean, core power request active-high | ||
- nvidia,sys-clock-req-active-high : Boolean, system clock request active-high | ||
- nvidia,combined-power-req : Boolean, combined power request for CPU & Core | ||
- nvidia,cpu-pwr-good-en : Boolean, CPU power good signal (from PMIC to PMC) | ||
is enabled. | ||
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Required properties when nvidia,suspend-mode is specified: | ||
- nvidia,cpu-pwr-good-time : CPU power good time in uS. | ||
- nvidia,cpu-pwr-off-time : CPU power off time in uS. | ||
- nvidia,core-pwr-good-time : <Oscillator-stable-time Power-stable-time> | ||
Core power good time in uS. | ||
- nvidia,core-pwr-off-time : Core power off time in uS. | ||
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Required properties when nvidia,suspend-mode=<0>: | ||
- nvidia,lp0-vec : <start length> Starting address and length of LP0 vector | ||
The LP0 vector contains the warm boot code that is executed by AVP when | ||
resuming from the LP0 state. The AVP (Audio-Video Processor) is an ARM7 | ||
processor and always being the first boot processor when chip is power on | ||
or resume from deep sleep mode. When the system is resumed from the deep | ||
sleep mode, the warm boot code will restore some PLLs, clocks and then | ||
bring up CPU0 for resuming the system. | ||
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Example: | ||
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/ SoC dts including file | ||
pmc@7000f400 { | ||
compatible = "nvidia,tegra20-pmc"; | ||
reg = <0x7000e400 0x400>; | ||
clocks = <&tegra_car 110>, <&clk32k_in>; | ||
clock-names = "pclk", "clk32k_in"; | ||
nvidia,invert-interrupt; | ||
nvidia,suspend-mode = <1>; | ||
nvidia,cpu-pwr-good-time = <2000>; | ||
nvidia,cpu-pwr-off-time = <100>; | ||
nvidia,core-pwr-good-time = <3845 3845>; | ||
nvidia,core-pwr-off-time = <458>; | ||
nvidia,core-power-req-active-high; | ||
nvidia,sys-clock-req-active-high; | ||
nvidia,lp0-vec = <0xbdffd000 0x2000>; | ||
}; | ||
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/ Tegra board dts file | ||
{ | ||
... | ||
clocks { | ||
compatible = "simple-bus"; | ||
#address-cells = <1>; | ||
#size-cells = <0>; | ||
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clk32k_in: clock { | ||
compatible = "fixed-clock"; | ||
reg=<0>; | ||
#clock-cells = <0>; | ||
clock-frequency = <32768>; | ||
}; | ||
}; | ||
... | ||
}; |
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Binding for the axi-clkgen clock generator | ||
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This binding uses the common clock binding[1]. | ||
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt | ||
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Required properties: | ||
- compatible : shall be "adi,axi-clkgen". | ||
- #clock-cells : from common clock binding; Should always be set to 0. | ||
- reg : Address and length of the axi-clkgen register set. | ||
- clocks : Phandle and clock specifier for the parent clock. | ||
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Optional properties: | ||
- clock-output-names : From common clock binding. | ||
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Example: | ||
clock@0xff000000 { | ||
compatible = "adi,axi-clkgen"; | ||
#clock-cells = <0>; | ||
reg = <0xff000000 0x1000>; | ||
clocks = <&osc 1>; | ||
}; |
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