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devicetree: bindings: Add documentation for HMC7044 driver
HMC7044 is a high performance, dual-loop, integer-N jitter attenuator capable of performing reference selection and generation of ultralow phase noise frequencies for high speed data converters with either parallel or serial (JESD204B type) interfaces. Signed-off-by: Dragos Bogdan <[email protected]>
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Documentation/devicetree/bindings/iio/frequency/hmc7044.txt
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| Analog Devices HMC7044 device driver | ||
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| Required properties: | ||
| - compatible: Should be "adi,hmc7044". | ||
| - reg: SPI chip select number. | ||
| - spi-max-frequency: Max SPI frequency to use (<= 10000000). | ||
| - adi,pll1-clkin-frequencies: An array of 4 elements, each | ||
| representing the frequency of CLKINx PLL1 reference | ||
| input (CLKIN0, CLKIN1, CLKIN2, CLKIN3). | ||
| - adi,vcxo-frequency: The frequency of the VCXO. | ||
| - adi,pll2-output-frequency: The desired output frequency of | ||
| the PLL2. | ||
| - adi,gpi-controls: An array of 4 elements (each corresponding | ||
| to GPI1, GPI2, GPI3 and GPI4, respectively), representing | ||
| the GPI selection (Bits [4:1]) and the GPI enable bit | ||
| ([0]) - see registers 0x0046, 0x0047, 0x0048, 0x0049. | ||
| - adi,gpo-controls: An array of 4 elements (each corresponding | ||
| to GPO1, GPO2, GPO3 and GPO4, respectively), representing | ||
| the GPO selection (Bits [7:2]), the GPO mode (Bit [1]) | ||
| and the GPO enable bit ([0]) - see registers 0x0050, | ||
| 0x0051, 0x0052, 0x0053. | ||
| - clock-output-names: An array of 14 elements, representing the | ||
| names of the output clocks. | ||
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| Optional properties: | ||
| - adi,pll1-loop-bandwidth-hz: The PLL1 loop bandwidth. If this is | ||
| not specified, 200 will be used by default. | ||
| - adi,sysref-timer-divider: This sets the internal beat frequency | ||
| of the master timer, which controls synchronization and | ||
| pulse generator events. It should be set to a submultiple | ||
| of the lowest output SYSREF frequency, no faster than 4 | ||
| MHz. If this is not specified, 1024 will be used by default. | ||
| - adi,pulse-generator-mode: Pulse Generator Mode Selection | ||
| [Bits 2:0] - see register 0x005A. If this is not specified, | ||
| 0 will be used by default. | ||
| - adi,clkin0-buffer-mode - CLKIN0 Input Buffer Control, for | ||
| specifing the Input Buffer Mode (Bits [4:1]) and the | ||
| Buffer enable bit ([0]) - see register 0x000A. If this is | ||
| not specified, 0 will be used by default. | ||
| - adi,clkin1-buffer-mode - CLKIN1 Input Buffer Control, for | ||
| specifing the Input Buffer Mode (Bits [4:1]) and the | ||
| Buffer enable bit ([0]) - see register 0x000B. If this is | ||
| not specified, 0 will be used by default. | ||
| - adi,clkin2-buffer-mode - CLKIN2 Input Buffer Control, for | ||
| specifing the Input Buffer Mode (Bits [4:1]) and the | ||
| Buffer enable bit ([0]) - see register 0x000C. If this is | ||
| not specified, 0 will be used by default. | ||
| - adi,clkin3-buffer-mode - CLKIN3 Input Buffer Control, for | ||
| specifing the Input Buffer Mode (Bits [4:1]) and the | ||
| Buffer enable bit ([0]) - see register 0x000D. If this is | ||
| not specified, 0 will be used by default. | ||
| - adi,oscin-buffer-mode - OSCIN Input Buffer Control, for | ||
| specifing the Input Buffer Mode (Bits [4:1]) and the | ||
| Buffer enable bit ([0]) - see register 0x000E. If this is | ||
| not specified, 0 will be used by default. | ||
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| Example: | ||
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| hmc7044: hmc7044@0 { | ||
| compatible = "adi,hmc7044"; | ||
| reg = <0>; | ||
| spi-max-frequency = <10000000>; | ||
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| adi,pll1-clkin-frequencies = <122880000 0 0 0>; | ||
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| adi,pll1-loop-bandwidth = <200>; | ||
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| adi,vcxo-frequency = <122880000>; | ||
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| adi,pll2-output-frequency = <2949120000>; | ||
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| adi,sysref-timer-divider = <1024>; | ||
| adi,pulse-generator-mode = <0>; | ||
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| adi,clkin0-buffer-mode = <0x15>; | ||
| adi,oscin-buffer-mode = <0x15>; | ||
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| adi,gpi-controls = <0x00 0x00 0x00 0x00>; | ||
| adi,gpo-controls = <0x1f 0x2b 0x00 0x00>; | ||
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| clock-output-names = "hmc7044_out0", "hmc7044_out1", "hmc7044_out2", | ||
| "hmc7044_out3", "hmc7044_out4", "hmc7044_out5", | ||
| "hmc7044_out6", "hmc7044_out7", "hmc7044_out8", | ||
| "hmc7044_out9", "hmc7044_out10", "hmc7044_out11", | ||
| "hmc7044_out12", "hmc7044_out13"; | ||
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| hmc7044_c2: channel@2 { | ||
| reg = <2>; | ||
| adi,extended-name = "DAC_CLK"; | ||
| adi,divider = <1>; | ||
| adi,driver-mode = <1>; | ||
| }; | ||
| hmc7044_c3: channel@3 { | ||
| reg = <3>; | ||
| adi,extended-name = "DAC_SYSREF"; | ||
| adi,divider = <512>; | ||
| adi,driver-mode = <1>; | ||
| }; | ||
| hmc7044_c12: channel@12 { | ||
| reg = <12>; | ||
| adi,extended-name = "FPGA_CLK"; | ||
| adi,divider = <8>; | ||
| adi,driver-mode = <2>; | ||
| }; | ||
| hmc7044_c13: channel@13 { | ||
| reg = <13>; | ||
| adi,extended-name = "FPGA_SYSREF"; | ||
| adi,divider = <512>; | ||
| adi,driver-mode = <2>; | ||
| }; | ||
| }; |