Merged dev into 2020

Makefile

@@ -120,7 +120,7 @@ autodata: check-autofpga
 	$(SUBMAKE) auto-data
 	$(call copyif-changed,auto-data/toplevel.v,rtl/toplevel.v)
 	$(call copyif-changed,auto-data/main.v,rtl/main.v)
-	$(call copyif-changed,auto-data/iscachable.v,rtl/cpu/iscachable.cpp)
+	$(call copyif-changed,auto-data/iscachable.v,rtl/cpu/iscachable.v)
 	$(call copyif-changed,auto-data/regdefs.h,sw/host/regdefs.h)
 	$(call copyif-changed,auto-data/regdefs.cpp,sw/host/regdefs.cpp)
 	$(call copyif-changed,auto-data/board.h,sw/zlib/board.h)

auto-data/Makefile

@@ -67,7 +67,7 @@ $(AUTOFPGA):
 
 .PHONY: data
 data: $(AUTOFPGA) $(DATA)
-	$(AUTOFPGA) -o . $(DATA)
+	$(AUTOFPGA) -d -o . $(DATA)
 
 clean:
 	rm -f toplevel.v main.v regdefs.h regdefs.cpp board.h board.ld

auto-data/busconsole.txt

@@ -45,6 +45,7 @@
 @ACCESS=WBUBUS_MASTER
 @MASTER.BUS=wbu
 @MASTER.TYPE=HOST
+@MASTER.PREFIX=@$(PREFIX)
 @BUS.NAME=wbu
 @BUS.CLOCK=clk
 @BUS.WIDTH=32

auto-data/mem_bkram_only.txt

@@ -2,7 +2,7 @@
 ##
 ## Filename: 	mem_flash_bkram.txt
 ##
-## Project:	OpenArty, an entirely open SoC based upon the Arty platform
+## Project:	ZBasic, a generic toplevel impl using the full ZipCPU
 ##
 ## Purpose:	Describes a memory model containing nothing more than flash
 ##		and block RAM.  This will be used to create a board.ld linker

auto-data/mem_flash_bkram.txt

@@ -2,7 +2,7 @@
 ##
 ## Filename: 	mem_flash_bkram.txt
 ##
-## Project:	OpenArty, an entirely open SoC based upon the Arty platform
+## Project:	ZBasic, a generic toplevel impl using the full ZipCPU
 ##
 ## Purpose:	Describes a memory model containing nothing more than flash
 ##		and block RAM.  This will be used to create a board.ld linker

auto-data/rtcdate.txt

@@ -42,11 +42,21 @@
 @DEPENDS=RTC_ACCESS
 @SLAVE.TYPE=SINGLE
 @SLAVE.BUS=wb
+@MAIN.PARAM=
+	//
+	// Initial calendar DATE
+	//
+`ifdef	VERSION_ACCESS
+	parameter	INITIAL_DATE = `DATESTAMP;
+`else
+	parameter	INITIAL_DATE = 30'h20000101;
+`endif
 @MAIN.INSERT=
 	//
 	// The Calendar DATE
 	//
-	rtcdate	@$(PREFIX)i(i_clk, rtc_ppd,
+	rtcdate	#(.INITIAL_DATE(INITIAL_DATE[29:0]))
+	@$(PREFIX)i(i_clk, rtc_ppd,
 		@$(SLAVE.PORTLIST));
 @REGS.N=1
 @REGS.0= 0 R_@$(DEVID) @$(DEVID) DATE

auto-data/rtclight.txt

@@ -81,3 +81,5 @@ typedef	struct	RTCLIGHT_S	{
 @RTL.MAKE.GROUP=@$(DEVID)
 @RTL.MAKE.SUBD=rtc
 @RTL.MAKE.FILES=rtclight.v rtcbare.v rtcalarm.v rtcstopwatch.v rtctimer.v
+##
+##

auto-data/sdspi.txt

@@ -49,19 +49,19 @@
 @SLAVE.TYPE=OTHER
 @SLAVE.BUS=wb
 @BUS.NAME=wb
-# @SCOPE.TRIGGER=sd_debug[31]
-# @SCOPE.DATA=sd_debug
+## @SCOPE.TRIGGER=sd_debug[31]
+## @SCOPE.DATA=sd_debug
 @INT.SDCARD.WIRE= @$(PREFIX)_int
 @INT.SDCARD.PIC= buspic syspic
 @TOP.PORTLIST=
 		// SD Card
-		o_sd_sck, io_sd_cmd, io_sd, i_sd_cd_n
+		o_sd_sck, io_sd_cmd, io_sd, i_sd_cd
 @TOP.IODECL=
 	// SD Card
 	output	wire		o_sd_sck;
 	inout	wire		io_sd_cmd;
 	inout	wire	[3:0]	io_sd;
-	input	wire		i_sd_cd_n;
+	input	wire		i_sd_cd;
 @TOP.DEFNS=
 	wire		w_sd_cmd;
 	wire	[3:0]	w_sd_data;
@@ -70,7 +70,7 @@
 	wire	[3:0]	i_sd;
 @TOP.MAIN=
 		// SD Card
-		o_sd_sck, w_sd_cmd, w_sd_data, i_sd_cmd, i_sd, !i_sd_cd_n
+		o_sd_sck, w_sd_cmd, w_sd_data, io_sd_cmd, io_sd, i_sd_cd
 @TOP.INSERT=
 	//
 	//

auto-data/version.txt

@@ -37,10 +37,11 @@
 ##
 @PREFIX=version
 @DEVID=VERSION
+@ACCESS=VERSION_ACCESS
 @NADDR=1
 @SLAVE.TYPE=SINGLE
 @SLAVE.BUS=wb
-@MAIN.DEFNS=
+@MAIN.INCLUDE=
 `include "builddate.v"
 @MAIN.INSERT=
 	assign	@$(SLAVE.PREFIX)_idata = `DATESTAMP;

auto-data/wbuart.txt

@@ -36,7 +36,7 @@
 ##
 ##
 # The prefix is used to create a series of bus data lines for interaction with
-# the bus.  In this case, these will be uart_sel, uart_ack, uart_stall, and
+# the bus.  In this case, these will be uart_sel, uart_stall, uart_ack, and
 # uart_data.
 @PREFIX=uart
 # The number of addressable registers this peripheral has on the wishbone bus.

auto-data/zipmaster.txt

@@ -43,6 +43,7 @@
 ##
 @SYSPIC= syspic
 @PREFIX=zip
+@SIM.CLOCK=clk
 @ACCESS=INCLUDE_ZIPCPU
 @DBGBUS=wbu
 @MASTER.TYPE=CPU

rtl/Makefile

@@ -59,16 +59,9 @@ VFLAGS = -Wall --MMD -O3 --trace -Mdir $(VDIRFB) $(AUTOVDIRS) -cc
 .PHONY: test auto-test
 test:	auto-test
 
-# .PHONY: hand-test
-# hand-test: $(VDIRFB)/Vbusmaster__ALL.a
-
 .PHONY: auto-test
 auto-test: $(VDIRFB)/Vmain__ALL.a
 
-$(VDIRFB)/Vbusmaster__ALL.a: $(VDIRFB)/Vbusmaster.h $(VDIRFB)/Vbusmaster.cpp
-$(VDIRFB)/Vbusmaster__ALL.a: $(VDIRFB)/Vbusmaster.mk
-$(VDIRFB)/Vbusmaster.h $(VDIRFB)/Vbusmaster.cpp $(VDIRFB)/Vbusmaster.mk: $(SOURCES)
-
 $(VDIRFB)/Vmain__ALL.a: $(VDIRFB)/Vmain.h $(VDIRFB)/Vmain.cpp
 $(VDIRFB)/Vmain__ALL.a: $(VDIRFB)/Vmain.mk
 

rtl/builddate.v

@@ -14,7 +14,7 @@
 //
 ////////////////////////////////////////////////////////////////////////////////
 //
-// Copyright (C) 2015-2019, Gisselquist Technology, LLC
+// Copyright (C) 2015-2020, Gisselquist Technology, LLC
 //
 // This program is free software (firmware): you can redistribute it and/or
 // modify it under the terms of  the GNU General Public License as published

rtl/cpu/iscachable.v

@@ -8,14 +8,14 @@
 // Computer Generated: This file is computer generated by AUTOFPGA. DO NOT EDIT.
 // DO NOT EDIT THIS FILE!
 //
-// CmdLine:	autofpga autofpga -o . global.txt bkram.txt buserr.txt clock.txt dlyarbiter.txt nflash.txt rtclight.txt rtcdate.txt pic.txt pwrcount.txt version.txt busconsole.txt zipmaster.txt sdspi.txt
+// CmdLine:	autofpga autofpga -d -o . clock.txt global.txt version.txt buserr.txt pic.txt pwrcount.txt gpio.txt rtclight.txt rtcdate.txt busconsole.txt bkram.txt flash.txt zipmaster.txt sdspi.txt mem_flash_bkram.txt mem_bkram_only.txt
 //
 // Creator:	Dan Gisselquist, Ph.D.
 //		Gisselquist Technology, LLC
 //
 ////////////////////////////////////////////////////////////////////////////////
 //
-// Copyright (C) 2017-2018, Gisselquist Technology, LLC
+// Copyright (C) 2017-2020, Gisselquist Technology, LLC
 //
 // This program is free software (firmware): you can redistribute it and/or
 // modify it under the terms of  the GNU General Public License as published
@@ -49,13 +49,12 @@ module iscachable(i_addr, o_cachable);
 	always @(*)
 	begin
 		o_cachable = 1'b0;
-		// Bus master: zip
 		// Bus master: wb
 		// Bus master: wb_sio
 		// bkram
-		if ((i_addr[22:0] & 23'h780000) == 23'h380000)
+		if ((i_addr[22:0] & 23'h780000) == 23'h300000)
 			o_cachable = 1'b1;
-		// nflash
+		// flash
 		if ((i_addr[22:0] & 23'h400000) == 23'h400000)
 			o_cachable = 1'b1;
 	end