HOTCHIPS conference code release

Updated code used for IEEE HOTCHIPS 2015 conference. LSU bus width between memory and register files has been significantly reduced to be synthesizable on FPGAs.

Known Issues:
Mismatch between wire/reg declaration and usage in sequential blocks. This primarily affects synthesis with Xilinx toolchains.
Current FPGA support framework does not work.
LSU lacks support for two and three dword operations.