Lint clean up

Szendvics · Jan 22, 2024 · 065aae1 · 065aae1
1 parent a9ba6e1
commit 065aae1
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Showing 5 changed files with 19 additions and 7 deletions.
diff --git a/rtl/bayer_dithering.v b/rtl/bayer_dithering.v
@@ -14,7 +14,6 @@
 `default_nettype none
 module bayer_dithering (
     input wire        clk,
-    input wire        rst,
     input wire [31:0] vin,
     output reg [15:0] vout,
     input wire [2:0]  x_pos,

diff --git a/rtl/blue_noise_dithering.v b/rtl/blue_noise_dithering.v
@@ -14,17 +14,18 @@
 `default_nettype none
 module blue_noise_dithering (
     input wire        clk,
-    input wire        rst,
     input wire [31:0] vin,
     output reg [15:0] vout,
     input wire [3:0]  x_pos,
     input wire [5:0]  y_pos
 );
-    parameter COLORMODE = "DES";
 
     wire [15:0] vo_dithered;
     wire [7:0] b0, b1, b2, b3;
+    /* verilator lint_off UNUSEDSIGNAL */
+    // Lower 4 bits are not used
     wire [7:0] c0, c1, c2, c3;
+    /* verilator lint_on UNUSEDSIGNAL */
 
     wire [9:0] addr_hi = {y_pos, x_pos};
 

diff --git a/rtl/caster.v b/rtl/caster.v
@@ -61,7 +61,10 @@ module caster(
     output wire [10:0]  dbg_scan_h_cnt
     );
 
+    /* verilator lint_off UNUSEDPARAM */
+    // Only used if bayer dithering is selected
     parameter COLORMODE = "MONO";
+    /* verilator lint_on UNUSEDPARAM */
 
     // Screen timing
     parameter SIMULATION = "TRUE";
@@ -71,7 +74,9 @@ module caster(
     localparam SCAN_WAITING = 2'd1;
     localparam SCAN_RUNNING = 2'd2;
 
+    /* verilator lint_off WIDTH */
     localparam OP_INIT_LENGTH = (SIMULATION == "FALSE") ? 255 : 2;
+    /* verilator lint_on WIDTH */
 
     // Internal design specific
     localparam VS_DELAY = 8; // wait 8 clocks after VS is vaild
@@ -357,6 +362,9 @@ module caster(
 
     // Image dithering
     wire [15:0] s2_pixel_ordered_dithered;
+
+    `ifndef USE_BLUE_NOISE
+    // Position for bayer dithering
     wire [2:0] x_pos;
     wire [2:0] y_pos;
 
@@ -397,6 +405,7 @@ module caster(
         assign y_pos = scan_v_cnt[2:0];
     end
     endgenerate
+    `endif
 
     // Degamma
     wire [31:0] s2_pixel_linear;
@@ -413,7 +422,6 @@ module caster(
     `ifdef USE_BLUE_NOISE
     blue_noise_dithering blue_noise_dithering (
         .clk(clk),
-        .rst(rst),
         .vin(s2_pixel_linear),
         .vout(s2_pixel_ordered_dithered),
         .x_pos(scan_h_cnt[3:0]),
@@ -424,7 +432,6 @@ module caster(
         .COLORMODE(COLORMODE)
     ) bayer_dithering (
         .clk(clk),
-        .rst(rst),
         .vin(s2_pixel_linear),
         .vout(s2_pixel_ordered_dithered),
         .x_pos(x_pos),

diff --git a/rtl/error_diffusion_kernel.v b/rtl/error_diffusion_kernel.v
@@ -1,4 +1,4 @@
-// Copyright Modos / Wenting Zhang 2023
+// Copyright Modos / Wenting Zhang 2024
 //
 // This source describes Open Hardware and is licensed under the CERN-OHL-P v2
 //
@@ -35,8 +35,10 @@ module error_diffusion_kernel #(
 );
 
     // Add input pixel with error
+    /* verilator lint_off UNUSEDSIGNAL */
     wire [ERROR_BITS+1-1:0] err_adder =
             $signed(err_left_in) + $signed(err_line_buffer_in);
+    /* verilator lint_on UNUSEDSIGNAL */
     wire [ERROR_BITS+1-1:0] pix_adder =
             $signed({{(ERROR_BITS-INPUT_BITS+1){1'b0}}, pixel_in}) +
             $signed(err_adder[ERROR_BITS+1-1:1]);
@@ -78,10 +80,12 @@ module error_diffusion_kernel #(
             $signed(pix_adder) - $signed({2'b0, pix_qlinear});
 
     // Distribute error
+    /* verilator lint_off UNUSEDSIGNAL */
     wire [ERROR_BITS+4-1:0] err_r_mult = $signed(quant_err) * 8;
     wire [ERROR_BITS+4-1:0] err_bl_mult = $signed(quant_err) * 3;
     wire [ERROR_BITS+4-1:0] err_b_mult = $signed(quant_err) * 4;
     wire [ERROR_BITS+4-1:0] err_br_mult = $signed(quant_err) * 1;
+    /* verilator lint_on UNUSEDSIGNAL */
     // Divide only by 8 (instead of 16) to get 10p1 fixed point format
     wire [ERROR_BITS+1-1:0] err_r_div = err_r_mult[ERROR_BITS+4-1:3];
     wire [ERROR_BITS+1-1:0] err_bl_div = err_bl_mult[ERROR_BITS+4-1:3];

diff --git a/sim/rtl.mk b/sim/rtl.mk
@@ -17,7 +17,8 @@ else
 VERILATOR := $(VERILATOR_ROOT)/bin/verilator
 endif
 VFLAGS := -Wall -Wno-fatal -MMD --trace -cc \
-		-I../rtl
+		-I../rtl \
+		-Wno-PINCONNECTEMPTY
 ifeq ($(VERBOSE), 1)
 VFLAGS += +define+VERBOSE=1
 endif