Added INIT_FILE parameter

RoaLogic · Oct 15, 2021 · 552bd78 · 552bd78
1 parent fee5c5d
commit 552bd78
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Showing 2 changed files with 17 additions and 4 deletions.
diff --git a/rtl/verilog/rl_ram_1rw.sv b/rtl/verilog/rl_ram_1rw.sv
@@ -69,7 +69,8 @@
 module rl_ram_1rw #(
   parameter ABITS      = 10,
   parameter DBITS      = 32,
-  parameter TECHNOLOGY = "GENERIC"
+  parameter TECHNOLOGY = "GENERIC",
+  parameter INIT_FILE  = ""
 )
 (
   input                    rst_ni,
@@ -115,8 +116,9 @@ generate
       initial $display ("INFO   : No memory technology specified. Using generic inferred memory (%m)");
 
       rl_ram_1rw_generic #(
-        .ABITS ( ABITS ),
-        .DBITS ( DBITS ) )
+        .ABITS     ( ABITS    ),
+        .DBITS     ( DBITS    ),
+        .INIT_FILE ( INIT_FILE) )
       ram_inst (
         .rst_ni ( rst_ni ),
         .clk_i  ( clk_i  ),

diff --git a/rtl/verilog/rl_ram_1rw_generic.sv b/rtl/verilog/rl_ram_1rw_generic.sv
@@ -66,7 +66,8 @@
 
 module rl_ram_1rw_generic #(
   parameter ABITS      = 10,
-  parameter DBITS      = 32
+  parameter DBITS      = 32,
+  parameter INIT_FILE  = ""
 )
 (
   input                        rst_ni,
@@ -94,6 +95,16 @@ module rl_ram_1rw_generic #(
   // Module Body
   //
 
+  //preload memory
+  //This seems to be synthesizable in FPGAs
+  initial
+    if (INIT_FILE != "")
+    begin
+        $display ("INFO   : Loading %s (%m)", INIT_FILE);
+        $readmemh(INIT_FILE, mem_array);
+    end
+
+
   //write side
 generate
   for (i=0; i<(DBITS+7)/8; i++)