Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

clockgate: set wireInit to avoid X in vcs simulation #69

Merged
merged 1 commit into from
Jun 14, 2024
Merged

clockgate: set wireInit to avoid X in vcs simulation #69

merged 1 commit into from
Jun 14, 2024

Conversation

Maxpicca-Li
Copy link
Member

  1. use WireInit for default initialization to avoid X in vcs simulation.
  2. In object GatedValidRegNext, change RegEnable to RegNext when it is applied to Bool due to two reasons.
    a. It is useless to clockgate only one bit.
    b. It is usually control signal. When last signal changed from X to 0 or 1, the old code RegEnable(next, init, next || last) would cause the next signal to take one more beat of X.

@Maxpicca-Li Maxpicca-Li merged commit 292a94d into master Jun 14, 2024
@Maxpicca-Li Maxpicca-Li deleted the fix-cg-X-240614 branch June 14, 2024 12:10
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Reviewers

@sumailyyc sumailyyc sumailyyc approved these changes

Assignees
No one assigned
Labels
None yet
Projects
None yet
Milestone
No milestone
Development

Successfully merging this pull request may close these issues.
2 participants
@Maxpicca-Li @sumailyyc