Adding sv struct and direct_port as defaults.

NVlabs · Sep 4, 2024 · 49416cf · 49416cf
1 parent 809b362
commit 49416cf
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Showing 6 changed files with 21 additions and 8 deletions.
diff --git a/cmod/cmod_Makefile b/cmod/cmod_Makefile
@@ -36,6 +36,9 @@ HLS_CATAPULT ?= 1
 ifeq ($(HLS_CATAPULT),1)
   CFLAGS += -DHLS_CATAPULT
 endif
+ifneq ($(findstring FORCE_AUTO_PORT,$(CFLAGS)),FORCE_AUTO_PORT)
+	CFLAGS += -DFORCE_AUTO_PORT=Connections::DIRECT_PORT
+endif
 
 LIBS ?=
 LIBS += -lstdc++ -lsystemc -lm -lpthread -lboost_timer -lboost_chrono -lboost_system

diff --git a/cmod/unittests/axi/AxiArbSplitTop/AxiArbSplitTop.h b/cmod/unittests/axi/AxiArbSplitTop/AxiArbSplitTop.h
@@ -51,7 +51,7 @@ class AxiArbSplitTop : public sc_module {
   axi_wr_slave_w axi_wr_m_w[numMasters];
   axi_wr_slave_b axi_wr_m_b[numMasters];
 
-  AxiArbiter<axi::cfg::standard, numSlaves, 16> axi_arbiter;
+  AxiArbiter<axi::cfg::standard, numMasters, 16> axi_arbiter;
 
   typename axi_::read::template chan<> axi_read_int;
   typename axi_::write::template chan<> axi_write_int;

diff --git a/hls/hls_Makefile b/hls/hls_Makefile
@@ -28,7 +28,7 @@ export HLS_CATAPULT   ?= 1
 export RUN_SCVERIFY   ?= 1
 export SYSTEMC_DESIGN ?= 1
 
-export RUN_CDESIGN_CHECKER	?= 0
+export RUN_CDESIGN_CHECKER ?= 0
 
 # Default compiler flags set by switches below.
 export COMPILER_FLAGS ?=
@@ -40,13 +40,19 @@ export COMPILER_FLAGS ?=
 # 2 = Faster TLM view of Connections port and channel code, CONNECTIONS_FAST_SIM.
 SIM_MODE ?= 1
 ifeq ($(SIM_MODE),0)
-	COMPILER_FLAGS += CONNECTIONS_SYN_SIM
+  COMPILER_FLAGS += CONNECTIONS_SYN_SIM
+  ifneq ($(findstring FORCE_AUTO_PORT,$(COMPILER_FLAGS)),FORCE_AUTO_PORT)
+    COMPILER_FLAGS += FORCE_AUTO_PORT=Connections::DIRECT_PORT
+  endif
 endif
 ifeq ($(SIM_MODE),1)
-	COMPILER_FLAGS += CONNECTIONS_ACCURATE_SIM SC_INCLUDE_DYNAMIC_PROCESSES
+  COMPILER_FLAGS += CONNECTIONS_ACCURATE_SIM SC_INCLUDE_DYNAMIC_PROCESSES
+  ifneq ($(findstring FORCE_AUTO_PORT,$(COMPILER_FLAGS)),FORCE_AUTO_PORT)
+    COMPILER_FLAGS += FORCE_AUTO_PORT=Connections::DIRECT_PORT
+  endif
 endif
 ifeq ($(SIM_MODE),2)
-	COMPILER_FLAGS += CONNECTIONS_FAST_SIM SC_INCLUDE_DYNAMIC_PROCESSES
+  COMPILER_FLAGS += CONNECTIONS_FAST_SIM SC_INCLUDE_DYNAMIC_PROCESSES
 endif
 
 
@@ -57,7 +63,7 @@ endif
 #   Note: Only valid if SIM_MODE = 1 (accurate) or 2 (fast)
 RAND_STALL ?= 0
 ifeq ($(RAND_STALL),1)
-	COMPILER_FLAGS += CONN_RAND_STALL
+  COMPILER_FLAGS += CONN_RAND_STALL
 endif
 
 DEBUG_LEVEL ?= 1

diff --git a/hls/nvhls_exec.tcl b/hls/nvhls_exec.tcl
@@ -55,7 +55,7 @@ namespace eval nvhls {
         go extract
 
         if { $RUN_SCVERIFY eq "1" } {
-          flow run /SCVerify/launch_make ./scverify/Verify_concat_sim_rtl_v_vcs.mk {} SIMTOOL=vcs sim
+          flow run /SCVerify/launch_make ./scverify/Verify_concat_sim_rtl_sv_vcs.mk {} SIMTOOL=vcs sim
         }
 
         project save

diff --git a/hls/run_hls_global_setup.tcl b/hls/run_hls_global_setup.tcl
@@ -95,3 +95,5 @@ directive set -CLUSTER_TYPE combinational
 directive set -COMPGRADE fast
 directive set -PIPELINE_RAMP_UP true
 directive set -CHAN_IO_PROTOCOL coupled
+directive set -PRESERVE_STRUCTS true
+directive set -STRUCT_LAYOUT c_style
diff --git a/hls/unittests/axi/AxiArbSplitTop/Makefile b/hls/unittests/axi/AxiArbSplitTop/Makefile
@@ -14,7 +14,9 @@
 #
 
 ROOT            := ../../../..
-SRC_PATH				:= $(ROOT)/cmod/unittests/axi
+SRC_PATH        := $(ROOT)/cmod/unittests/axi
+
+COMPILER_FLAGS += FORCE_AUTO_PORT=Connections::MARSHALL_PORT
 
 include $(ROOT)/hls/hls_Makefile