A minimal GPU design in Verilog to learn how GPUs work from the ground up

程序员在家做饭方法指南。Programmer's guide about how to cook at home (Simplified Chinese only).

RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni

Stable Diffusion web UI

Fast C++ logging library.

RTL, Cmodel, and testbench for NVDLA

Network on Chip Simulator

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

scikit-learn: machine learning in Python

PPL Quantization Tool (PPQ) is a powerful offline neural network quantization tool.

Network Analysis in Python

A collection of pre-trained, state-of-the-art models in the ONNX format

pytorch to caffe by onnx

Tutorials for creating and using ONNX models

Systolic Three Matrix Multiplier for Graph Convolutional Networks using High Level Synthesis

DUTH RISC V Microprocessor for High Level Synthesis

HLS for Networks-on-Chip

A CNN model to to recognize Japanese adult video actress face

A Behavior-Level Modeling Tool for Memristor-based Neuromorphic Computing Systems

A multithreaded Minecraft server built for redstone.

Genetic Algorithm, Particle Swarm Optimization, Simulated Annealing, Ant Colony Optimization Algorithm,Immune Algorithm, Artificial Fish Swarm Algorithm, Differential Evolution and TSP(Traveling sa…

Open-source high-performance RISC-V processor

🚀AI拟声: 5秒内克隆您的声音并生成任意语音内容 Clone a voice in 5 seconds to generate arbitrary speech in real-time

Reimplementation ResNet on cifar10 with caffe

Proper implementation of ResNet-s for CIFAR10/100 in pytorch that matches description of the original paper.

Practice on cifar100(ResNet, DenseNet, VGG, GoogleNet, InceptionV3, InceptionV4, Inception-ResNetv2, Xception, Resnet In Resnet, ResNext,ShuffleNet, ShuffleNetv2, MobileNet, MobileNetv2, SqueezeNet…

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