setting license as CERN OHL

updating titleblocks ready for 1.0 release, added silkscreen ID & version.
changed from 4V-70V to 5V-60V to reflect design capabilities
changed R1 from 1k to 3k6 & removed text note
added description, manufacturer, part number & supplier info for all RS parts
added TODO text doc

LICENSE.md

@@ -1,3 +1,2 @@
-TBD - possibly CERN OSHW license?
+CERN Open Hardware License Version 1.2, or later.
 http://www.ohwr.org/licenses/cern-ohl/v1.2
-Undecided; private copyrighted work until updated.

README.md

@@ -1 +1 @@
-20A 4V-80V Ideal Diode
+20A 5V-60V Ideal Diode

TODO.txt

@@ -0,0 +1,27 @@
+FOR V1.0
+still need to add part info for commodity R's and header P1
+need to sort out BOM export plugin & target format
+find out why silkscreen refdes dont look visible
+complete readme
+
+
+FOR V2.0
+Test! (20A continuous, step response, reverse & overvoltage protection, input/output shorts)
+move P1 away from GND1 hole
+add thermal relief on C1, C2, R1, R4 etc
+silkscreen on /SHDN header P1 describing
+move FETs upwards & centre IN/OUT holes to FETs
+make for M4 bolts (incl bigger pads), leave enough clearance for ring crimp terminals
+move bottom half compoents slightly to left to give even space
+make whole PCB taller - square? to give better thermal, lower resistance etc
+dont need 1M pullup resistor!
+be very careful when soldering, must have damaged LTC4359 before! Solder Q1 Q2 first.
+LTC4359I only 85C (125C for H version), cut plane back slightly & move FETS upwards to stop heating up? Consider H version.
+silkscreen to show big diode for main function - bottom? also for big +ve and -ve signs
+possibly use larger R1 value, but smaller case size. Sacrifices some of the minimum voltage to reduce power in component during reverse protection fault
+option to BOM fit change to BSC016N06NSATMA1 fets for 1.5mohm instead of 2.5mohm Rdson
+Change from 60V protection to 70V to allow higher input voltage?
+remove second ground hole and just have single? removes dissipation in  GND tracks & two ring terminals could be attached on one hole
+
+put on kitnic, get 10off(?) PCBs & advertise
+advertise e.g. motorhome group on facebook

kitnic.yaml

@@ -1,4 +1,4 @@
-description: 20A 4V-80V Ideal Diode circuit based on the Linear Tech LT4359
+description: 20A 5V-60V Ideal Diode circuit based on the Linear Tech LT4359
 site: http://www.inanecoding.co.uk
 color: green
 bom: pcb/1-click-BOM.tsv

pcb/ideal_diode-cache.lib

@@ -13,31 +13,31 @@ C -150 75 5 0 0 0 N
 C -50 75 5 0 0 0 N
 C 50 75 5 0 0 0 N
 C 150 75 5 0 0 0 N
-T 0 125 100 30 0 0 0 D  Normal 0 C C
-T 0 -20 -120 30 0 0 0 G  Normal 0 C C
-T 0 -125 100 30 0 0 0 S  Normal 0 C C
-P 2 0 0 0  -200 100  -150 100 N
-P 2 0 0 0  -50 75  -150 75 N
-P 2 0 0 0  200 100  150 100 N
-P 4 0 0 0  -50 25  -50 110  50 110  50 25 N
-P 4 0 0 0  5 110  -15 120  -15 100  5 110 F
-P 4 0 0 0  15 125  10 120  10 100  5 95 N
+T 0 125 100 30 0 0 0 D Normal 0 C C
+T 0 -20 -120 30 0 0 0 G Normal 0 C C
+T 0 -125 100 30 0 0 0 S Normal 0 C C
+P 2 0 0 0 -200 100 -150 100 N
+P 2 0 0 0 -50 75 -150 75 N
+P 2 0 0 0 200 100 150 100 N
+P 4 0 0 0 -50 25 -50 110 50 110 50 25 N
+P 4 0 0 0 5 110 -15 120 -15 100 5 110 F
+P 4 0 0 0 15 125 10 120 10 100 5 95 N
 C -150 100 5 0 1 0 N
 C 0 50 111 0 1 8 N
 C 150 0 5 0 1 0 N
 C 150 100 5 0 1 0 N
 S -200 250 200 -200 0 1 10 f
-P 2 0 1 15  -65 25  -35 25 N
-P 2 0 1 15  -15 25  15 25 N
-P 2 0 1 0  0 0  0 -200 N
-P 2 0 1 15  35 25  65 25 N
-P 2 0 1 0  50 75  150 75 N
-P 2 0 1 0  200 0  150 0 N
-P 3 0 1 10  -60 0  60 0  60 0 N
-P 3 0 1 0  0 25  0 75  -50 75 N
-P 4 0 1 0  -200 0  -150 0  -150 200  -200 200 N
-P 4 0 1 0  -10 65  10 65  0 40  -10 65 F
-P 4 0 1 0  200 200  150 200  150 -100  200 -100 N
+P 2 0 1 15 -65 25 -35 25 N
+P 2 0 1 15 -15 25 15 25 N
+P 2 0 1 0 0 0 0 -200 N
+P 2 0 1 15 35 25 65 25 N
+P 2 0 1 0 50 75 150 75 N
+P 2 0 1 0 200 0 150 0 N
+P 3 0 1 10 -60 0 60 0 60 0 N
+P 3 0 1 0 0 25 0 75 -50 75 N
+P 4 0 1 0 -200 0 -150 0 -150 200 -200 200 N
+P 4 0 1 0 -10 65 10 65 0 40 -10 65 F
+P 4 0 1 0 200 200 150 200 150 -100 200 -100 N
 X S 1 -300 200 100 R 50 50 1 1 P
 X S 2 -300 100 100 R 50 50 1 1 P
 X S 3 -300 0 100 R 50 50 1 1 P
@@ -64,8 +64,8 @@ $FPLIST
  Capacitor*
 $ENDFPLIST
 DRAW
-P 2 0 1 20  -80 -30  80 -30 N
-P 2 0 1 20  -80 30  80 30 N
+P 2 0 1 20 -80 -30 80 -30 N
+P 2 0 1 20 -80 30 80 30 N
 X ~ 1 0 150 110 D 40 40 1 1 P
 X ~ 2 0 -150 110 U 40 40 1 1 P
 ENDDRAW
@@ -123,7 +123,7 @@ F1 "GND" 0 -150 50 H V C CNN
 F2 "" 0 0 50 H V C CNN
 F3 "" 0 0 50 H V C CNN
 DRAW
-P 6 0 1 0  0 0  0 -50  50 -50  0 -100  -50 -50  0 -50 N
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
 X GND 1 0 0 0 D 50 50 1 1 W N
 ENDDRAW
 ENDDEF
@@ -181,8 +181,8 @@ $FPLIST
  SM*
 $ENDFPLIST
 DRAW
-P 5 0 1 8  -70 50  -50 30  -50 -30  -30 -50  -30 -50 N
-P 5 0 1 0  -50 0  50 50  50 -50  -50 0  -50 0 F
+P 5 0 1 8 -70 50 -50 30 -50 -30 -30 -50 -30 -50 N
+P 5 0 1 0 -50 0 50 50 50 -50 -50 0 -50 0 F
 X K 1 -200 0 150 R 50 50 1 1 P
 X A 2 200 0 150 L 50 50 1 1 P
 ENDDRAW

pcb/ideal_diode.kicad_pcb

@@ -1,11 +1,11 @@
-(kicad_pcb (version 4) (host pcbnew 4.0.1-stable)
+(kicad_pcb (version 4) (host pcbnew 4.0.4-stable)
 
   (general
     (links 100)
     (no_connects 0)
-    (area 114.091667 85.472619 182.458334 122.775)
+    (area 114.166667 85.547619 182.383334 122.875)
     (thickness 1.6)
-    (drawings 8)
+    (drawings 9)
     (tracks 64)
     (zones 0)
     (modules 76)
@@ -14,9 +14,9 @@
 
   (page A4)
   (title_block
-    (title "20A Ideal Diode LTC4359 4V-70V")
-    (date 2016-01-22)
-    (rev 0.9)
+    (title "20A Ideal Diode LTC4359 5V-60V")
+    (date 2016-12-10)
+    (rev 1.0)
   )
 
   (layers
@@ -70,7 +70,7 @@
     (pad_to_mask_clearance 0.1)
     (solder_mask_min_width 0.1)
     (aux_axis_origin 129.3 113.8)
-    (visible_elements 7FFFFFFF)
+    (visible_elements 7FFFFFDF)
     (pcbplotparams
       (layerselection 0x010e8_80000001)
       (usegerberextensions true)
@@ -1440,6 +1440,9 @@
       (net 8 /SOURCE))
   )
 
+  (gr_text "KOS01\nv1.0" (at 134.62 99.06) (layer F.SilkS)
+    (effects (font (size 1.5 1.5) (thickness 0.3)))
+  )
   (gr_line (start 130.3 112.8) (end 162.3 112.8) (angle 90) (layer Margin) (width 0.2))
   (gr_line (start 130.3 89.8) (end 130.3 112.8) (angle 90) (layer Margin) (width 0.2))
   (gr_line (start 162.3 89.8) (end 130.3 89.8) (angle 90) (layer Margin) (width 0.2))

pcb/ideal_diode.pro

@@ -1,4 +1,4 @@
-update=2016/01/16 16:01:03
+update=10/12/2016 15:20:53
 version=1
 last_client=kicad
 [pcbnew]
@@ -27,7 +27,7 @@ NetIExt=net
 version=1
 [eeschema]
 version=1
-LibDir=C:/freelance/kicad_library/schematic
+LibDir=D:/freelance/kicad_library/schematic
 [eeschema/libraries]
 LibName1=_kb
 LibName2=power