The SpinalHDL design of the Proteus core, an extensible RISC-V core.

RISC-V port of newlib

Official OpenOCD Read-Only Mirror (no pull requests)

Learning how to make a RISC-V

Free collection of hardware modules written in Verilog for FPGAs and embedded systems.

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

RISC-VのCPU作った

RISC V core implementation using Verilog.

A RISC-V SBC based around the LambdaConcept USB2Sniffer FPGA board.

Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).

phoeniX RISC-V Processor

A simple RISC-V CPU written in Verilog.

Another tiny RISC-V implementation

体系结构课程实验：RISC-V 32I 流水线 CPU，实现37条指令，转发，冒险检测，Cache，分支预测器

This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover

RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

PicoRV32 - A Size-Optimized RISC-V CPU

RISC-V CPU Core (RV32IM)

The Ultra-Low Power RISC-V Core

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

A curated list of awesome Go frameworks, libraries and software

High performance, distributed and low latency publish-subscribe platform.

a small build system with a focus on speed

Delve is a debugger for the Go programming language.

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

ML305A_ML307A_OpenCPU_Standard_1.4.2.2023062518_release

A portable MQTT C client for embedded systems and PCs alike.

paho.mqtt.javascript

NodeSource Node.js Binary Distributions