implementation of a machine executes simple operations in general built-in registers in Verilog
-
Updated
Jan 23, 2020 - Verilog
implementation of a machine executes simple operations in general built-in registers in Verilog
🎓💻University of Tehran Digital Logic Design Course Projects - Fall 2020
Clock and UART Baud rate generation, radix-4 multiplier, function generator & accelerator wrappers.
DLD Project - A simple vending machine simulation with Verilog (Spring 2024)
11020EECS101002
Digital logic 📐 assignments for module: CSU11026
Undegraduate Capstone Project - Spring'21 (VIT University).
Controlling a simple traffic light system.
Projects of the digital logic design lab (Fall01) at the University of Tehran.
sequence detector with overlapped 2 patterns 010111 or 1101
32-bit Divider circuit implemented using Verilog
🎓💻University of Tehran Digital Logic Design Lab Course Projects - Spring 2021
This repository contain basic verilog codes which include the implementation of DLD (digital logic desgin ) circuits.
EECS207001
Clock and UART Baud rate generation, radix-4 multiplier, function generator & accelerator wrappers.
透過數位邏輯結合VHDL與Verilog的過程,作為從基礎數位邏輯到計算機系統結構,並實作出一顆CPU的教學書籍,希望未來可以成為教學範例檔案。目前將開發轉移到GitLab,因為可以呈現數學與MUL圖。
Add a description, image, and links to the digital-logic-design topic page so that developers can more easily learn about it.
To associate your repository with the digital-logic-design topic, visit your repo's landing page and select "manage topics."