Improve the new Verilog compiler UI and error reporting

[tomcl]

Try using the new compiler (under Verilog). Add your list of confusing things.

Here is my list of things that could be improved:

The Example: -

• It should be cut and pastable into the edit window.
• There should be a more varied set of syntax - e.g. literals
• Maybe there should be multiple examples, it must be easy to find an example of every supported construct
• There should somehow be a list of all supported syntax.

More difficult but doable:

The compiler & lexer. Change lexing and parsing of literals so that the "help" messages for literals are better.

Not sure how to do:

Add examples to help? Or some way to turn compiler syntax clauses into specific examples? Not sure.