elementary logic gates

.gitignore

@@ -0,0 +1 @@
+*.out

01-bool_fns_and_gate_logic/logic-gates/1-elementary/1-Not/Not.hdl → 01-logic_gates/1-elementary/1-Not/Not.hdl

@@ -13,5 +13,5 @@ CHIP Not {
     OUT out;
 
     PARTS:
-    // Put your code here:
+    Nand(a=in, b=in, out=out);
 }

01-bool_fns_and_gate_logic/logic-gates/1-elementary/2-And/And.hdl → 01-logic_gates/1-elementary/2-And/And.hdl

@@ -14,5 +14,6 @@ CHIP And {
     OUT out;
 
     PARTS:
-    // Put your code here:
+    Nand(a=a, b=b, out=aNandb);
+    Not(in=aNandb, out=out);
 }

01-bool_fns_and_gate_logic/logic-gates/1-elementary/3-Or/Or.hdl → 01-logic_gates/1-elementary/3-Or/Or.hdl

@@ -14,5 +14,8 @@ CHIP Or {
     OUT out;
 
     PARTS:
-    // Put your code here:
+    Not(in=a, out=Nota);
+    Not(in=b, out=Notb);
+    And(a=Nota, b=Notb, out=NotaAndNotb);
+    Not(in=NotaAndNotb, out=out);
 }

01-bool_fns_and_gate_logic/logic-gates/1-elementary/4-Xor/Xor.hdl → 01-logic_gates/1-elementary/4-Xor/Xor.hdl

@@ -13,5 +13,9 @@ CHIP Xor {
     OUT out;
 
     PARTS:
-    // Put your code here:
+    Not(in=a, out=Nota);
+    Not(in=b, out=Notb);
+    And(a=a, b=Notb, out=aAndNotb);
+    And(a=Nota, b=b, out=NotaAndb);
+    Or(a=aAndNotb, b=NotaAndb, out=out);
 }

01-bool_fns_and_gate_logic/logic-gates/1-elementary/5-Mux/Mux.hdl → 01-logic_gates/1-elementary/5-Mux/Mux.hdl

@@ -14,5 +14,8 @@ CHIP Mux {
     OUT out;
 
     PARTS:
-    // Put your code here:
+    Not(in=sel, out=Notsel);
+    And(a=a, b=Notsel, out=sela);
+    And(a=sel, b=b, out=selb);
+    Or(a=sela, b=selb, out=out);
 }

01-bool_fns_and_gate_logic/logic-gates/1-elementary/6-DMux/DMux.hdl → 01-logic_gates/1-elementary/6-DMux/DMux.hdl

@@ -14,5 +14,7 @@ CHIP DMux {
     OUT a, b;
 
     PARTS:
-    // Put your code here:
-}
+    Not(in=sel, out=Notsel);
+    And(a=in, b=Notsel, out=a);
+    And(a=in, b=sel, out=b);
+}