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Commits on Apr 10, 2020

• Make TooManyHwbp more thorough. (riscv-software-src#272)

  timsifive

  committedApr 10, 2020
  2a869e0

• Change slen to a value that spike supports. (riscv-software-src#271)

  timsifive

  committedApr 10, 2020
  f2107b6

Commits on Mar 30, 2020

• Add debug-check-fast target for

  aswaterman

  committedMar 30, 2020
  19bfdab

Commits on Mar 26, 2020

• Improve address translation tests (riscv-software-src#261)

  timsifive

  committedMar 26, 2020
  7351b31

• Write a NOP program in PrivRw test. (riscv-software-src#260)

  timsifive

  committedMar 26, 2020
  094985d

Commits on Mar 21, 2020

• Fix regression introduced by 24d7d6b

  aswaterman

  committedMar 21, 2020
  5fe6092

• Move self-modifying 'fence.i' ops to .data memory section (riscv-software-src#269)

  

  WRansohoff

  and

  WRR

  committedMar 21, 2020
  8333b4f

Commits on Mar 19, 2020

• Fix comments error in fmin.S (riscv-software-src#267)

  mohanson

  committedMar 19, 2020
  08cbae4

Commits on Mar 18, 2020

• Spike changed --varch syntax (riscv-software-src#257)

  timsifive

  committedMar 18, 2020
  6c53e59

• Specify misa for HiFive Unleashed. (riscv-software-src#259)

  timsifive

  committedMar 18, 2020
  b436c73

• Have both rs=rd and rs!=rd cases in csr.S (riscv-software-src#263)

  takahirox

  committedMar 18, 2020
  24d7d6b

• Fix shamt.S header (riscv-software-src#264)

  takahirox

  committedMar 18, 2020
  f04e824

Commits on Mar 16, 2020

• Add a test case rs = rd to jalr.S (riscv-software-src#258)

  takahirox

  committedMar 16, 2020
  b59b7b8

Commits on Mar 11, 2020

• Add comment explaining convoluted rv64mi-p-scall behavior

  aswaterman

  committedMar 11, 2020
  272093f

• Revert "scall: make the intention of the test in machine mode more clear (riscv-software-src#246)"

  aswaterman

  committedMar 11, 2020
  ee576c0

• Setup a multilevel page table to avoid misaligned superpages caused by variable DRAM_BASE (riscv-software-src#255)

  cedric-orban

  committedMar 11, 2020
  72d284b

Commits on Mar 7, 2020

• Don't assume reset state of mscratch (riscv-software-src#254)

  pdonahue-ventana

  committedMar 7, 2020
  60e314e

Commits on Mar 6, 2020

• bump env (riscv-software-src#253)

  HanKuanChen

  committedMar 6, 2020
  0ab4c3c

• Bump riscv-test-env (riscv-software-src#252)

  aswaterman

  committedMar 6, 2020
  b751373

Commits on Mar 5, 2020

• Clean up gdb parsing code. (riscv-software-src#247)

  timsifive

  committedMar 5, 2020
  3109b4d

• Add a simple mechanism to skip tests on targets. (riscv-software-src#251)

  timsifive

  committedMar 5, 2020
  34b02fd

Commits on Mar 3, 2020

• enable rv32e compatability by replacing reg x29 with reg x7 (riscv-software-src#250)

  cedric-orban

  committedMar 3, 2020
  fb0510f

Commits on Feb 28, 2020

• bump env

  aswaterman

  committedFeb 28, 2020
  a46bbcf

Commits on Feb 21, 2020

• scall: make the intention of the test in machine mode more clear (riscv-software-src#246)

  Nils-TUD

  committedFeb 21, 2020
  6fa1896

Commits on Feb 20, 2020

• Fix rv64mi-p-csr on systems with FPUs

  aswaterman

  committedFeb 20, 2020
  b6f7299

Commits on Feb 14, 2020

• Add tests for vector register access (riscv-software-src#244)

  timsifive

  committedFeb 14, 2020
  10706c5

Commits on Feb 11, 2020

• Generate very different values on different harts. (riscv-software-src#238)

  timsifive

  committedFeb 11, 2020
  abfa60c

• Run OpenOCD output through spike-dasm. (riscv-software-src#239)

  timsifive

  committedFeb 11, 2020
  43b02e6

• Look for \bmain\b instead of ' main '. (riscv-software-src#237)

  timsifive

  committedFeb 11, 2020
  67af8d6

Commits on Feb 8, 2020

• Solves riscv-software-src#241 : Each mhartid has the same size of stack & TLS. (riscv-software-src#242)

  laysakura

  committedFeb 8, 2020
  0796441

Commits on Jan 31, 2020

• Added CSR test cases on whether writing 0 to CSR works, as that might get overlooked by implementors because some CSR operations should ignore writes if source is x0 (riscv-software-src#236)

  tovine

  committedJan 31, 2020
  3a98ec2

Commits on Jan 15, 2020

• Force DMI busy in all tests. (riscv-software-src#235)

  timsifive

  committedJan 15, 2020
  32274e0

Commits on Jan 9, 2020

• Smoke test virtual address translation support. (riscv-software-src#233)

  timsifive

  committedJan 9, 2020
  6db6ab8

Commits on Dec 28, 2019

• benchmarks: Disassemble .text.init section (riscv-software-src#230)

  

  a0u

  authored and

  aswaterman

  committedDec 28, 2019
  d081949

Commits on Dec 24, 2019

• submodule: bump env version (riscv-software-src#229)

  

  chihminchao

  authored and

  aswaterman

  committedDec 24, 2019
  b757ff0

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