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FIR filter implementation

中文版 Parallel Programming for FPGAs

HLS Project of pp4fpgas - https://github.com/xupsh/pp4fpgas-cn

A zero-copy Linux driver and a userspace interface library for Xilinx's AXI DMA and VDMA IP blocks. These serve as bridges for communication between the processing system and FPGA programmable logi…

An Synthesizable Deep Learning Library based on Xilinx High Level Synthesis(HLS) tool

Machine learning on FPGAs using HLS

This project implemented an unoptimized simple convolutional neural network in ZYNQ's PL and realized data transmission through axidma driver on Linux.

Master Thesis "ZynqNet: An FPGA-Accelerated Embedded Convolutional Neural Network"

Convolutional Neural Network Using High Level Synthesis