RTL, Cmodel, and testbench for NVDLA

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

SERV - The SErial RISC-V CPU

Verilog library for ASIC and FPGA designers

OpenXuantie - OpenC910 Core

An Open-source FPGA IP Generator

Source and Documentation files for USB C Industrial Camera Project, This repo contains PCB boards, FPGA , Camera and USB along with FPGA Firmware and USB Controller Firmware source.

3-stage RV32IMACZb* processor with debug

A High-performance Timing Analysis Tool for VLSI Systems

Project Apicula 🐝: bitstream documentation for Gowin FPGAs

iCESugar FPGA Board (base on iCE40UP5k)

OpenXuantie - OpenC906 Core

RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)

FuseSoC-based SoC for VeeR EH1 and EL2

Chisel implementation of the NVIDIA Deep Learning Accelerator (NVDLA), with self-driving accelerated

Macro Placement - benchmarks, evaluators, and reproducible results from leading methods in open source

SystemC/TLM-2.0 Co-simulation framework

A full-speed device-side USB peripheral core written in Verilog.

RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT

EPFL logic synthesis benchmarks

OpenXuantie - OpenE902 Core

OpenXuantie - OpenE906 Core

Chisel components for FPGA projects

Xilinx Unisim Library in Verilog

Vortex Graphics

The source code to the Voss II Hardware Verification Suite

Parameterized Booth Multiplier in Verilog 2001

Original RISC-V 1.0 implementation. Not supported.