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cvmx-pow.h
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cvmx-pow.h
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/***********************license start***************
* Author: Cavium Networks
*
* Contact: [email protected]
* This file is part of the OCTEON SDK
*
* Copyright (c) 2003-2008 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
* published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful, but
* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
* NONINFRINGEMENT. See the GNU General Public License for more
* details.
*
* You should have received a copy of the GNU General Public License
* along with this file; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* or visit http://www.gnu.org/licenses/.
*
* This file may also be available under a different license from Cavium.
* Contact Cavium Networks for more information
***********************license end**************************************/
/**
* Interface to the hardware Packet Order / Work unit.
*
* New, starting with SDK 1.7.0, cvmx-pow supports a number of
* extended consistency checks. The define
* CVMX_ENABLE_POW_CHECKS controls the runtime insertion of POW
* internal state checks to find common programming errors. If
* CVMX_ENABLE_POW_CHECKS is not defined, checks are by default
* enabled. For example, cvmx-pow will check for the following
* program errors or POW state inconsistency.
* - Requesting a POW operation with an active tag switch in
* progress.
* - Waiting for a tag switch to complete for an excessively
* long period. This is normally a sign of an error in locking
* causing deadlock.
* - Illegal tag switches from NULL_NULL.
* - Illegal tag switches from NULL.
* - Illegal deschedule request.
* - WQE pointer not matching the one attached to the core by
* the POW.
*
*/
#ifndef __CVMX_POW_H__
#define __CVMX_POW_H__
#include <asm/octeon/cvmx-pow-defs.h>
#include "cvmx-scratch.h"
#include "cvmx-wqe.h"
/* Default to having all POW constancy checks turned on */
#ifndef CVMX_ENABLE_POW_CHECKS
#define CVMX_ENABLE_POW_CHECKS 1
#endif
enum cvmx_pow_tag_type {
/* Tag ordering is maintained */
CVMX_POW_TAG_TYPE_ORDERED = 0L,
/* Tag ordering is maintained, and at most one PP has the tag */
CVMX_POW_TAG_TYPE_ATOMIC = 1L,
/*
* The work queue entry from the order - NEVER tag switch from
* NULL to NULL
*/
CVMX_POW_TAG_TYPE_NULL = 2L,
/* A tag switch to NULL, and there is no space reserved in POW
* - NEVER tag switch to NULL_NULL
* - NEVER tag switch from NULL_NULL
* - NULL_NULL is entered at the beginning of time and on a deschedule.
* - NULL_NULL can be exited by a new work request. A NULL_SWITCH
* load can also switch the state to NULL
*/
CVMX_POW_TAG_TYPE_NULL_NULL = 3L
};
/**
* Wait flag values for pow functions.
*/
typedef enum {
CVMX_POW_WAIT = 1,
CVMX_POW_NO_WAIT = 0,
} cvmx_pow_wait_t;
/**
* POW tag operations. These are used in the data stored to the POW.
*/
typedef enum {
/*
* switch the tag (only) for this PP
* - the previous tag should be non-NULL in this case
* - tag switch response required
* - fields used: op, type, tag
*/
CVMX_POW_TAG_OP_SWTAG = 0L,
/*
* switch the tag for this PP, with full information
* - this should be used when the previous tag is NULL
* - tag switch response required
* - fields used: address, op, grp, type, tag
*/
CVMX_POW_TAG_OP_SWTAG_FULL = 1L,
/*
* switch the tag (and/or group) for this PP and de-schedule
* - OK to keep the tag the same and only change the group
* - fields used: op, no_sched, grp, type, tag
*/
CVMX_POW_TAG_OP_SWTAG_DESCH = 2L,
/*
* just de-schedule
* - fields used: op, no_sched
*/
CVMX_POW_TAG_OP_DESCH = 3L,
/*
* create an entirely new work queue entry
* - fields used: address, op, qos, grp, type, tag
*/
CVMX_POW_TAG_OP_ADDWQ = 4L,
/*
* just update the work queue pointer and grp for this PP
* - fields used: address, op, grp
*/
CVMX_POW_TAG_OP_UPDATE_WQP_GRP = 5L,
/*
* set the no_sched bit on the de-schedule list
*
* - does nothing if the selected entry is not on the
* de-schedule list
*
* - does nothing if the stored work queue pointer does not
* match the address field
*
* - fields used: address, index, op
*
* Before issuing a *_NSCHED operation, SW must guarantee
* that all prior deschedules and set/clr NSCHED operations
* are complete and all prior switches are complete. The
* hardware provides the opsdone bit and swdone bit for SW
* polling. After issuing a *_NSCHED operation, SW must
* guarantee that the set/clr NSCHED is complete before any
* subsequent operations.
*/
CVMX_POW_TAG_OP_SET_NSCHED = 6L,
/*
* clears the no_sched bit on the de-schedule list
*
* - does nothing if the selected entry is not on the
* de-schedule list
*
* - does nothing if the stored work queue pointer does not
* match the address field
*
* - fields used: address, index, op
*
* Before issuing a *_NSCHED operation, SW must guarantee that
* all prior deschedules and set/clr NSCHED operations are
* complete and all prior switches are complete. The hardware
* provides the opsdone bit and swdone bit for SW
* polling. After issuing a *_NSCHED operation, SW must
* guarantee that the set/clr NSCHED is complete before any
* subsequent operations.
*/
CVMX_POW_TAG_OP_CLR_NSCHED = 7L,
/* do nothing */
CVMX_POW_TAG_OP_NOP = 15L
} cvmx_pow_tag_op_t;
/**
* This structure defines the store data on a store to POW
*/
typedef union {
uint64_t u64;
struct {
/*
* Don't reschedule this entry. no_sched is used for
* CVMX_POW_TAG_OP_SWTAG_DESCH and
* CVMX_POW_TAG_OP_DESCH
*/
uint64_t no_sched:1;
uint64_t unused:2;
/* Tontains index of entry for a CVMX_POW_TAG_OP_*_NSCHED */
uint64_t index:13;
/* The operation to perform */
cvmx_pow_tag_op_t op:4;
uint64_t unused2:2;
/*
* The QOS level for the packet. qos is only used for
* CVMX_POW_TAG_OP_ADDWQ
*/
uint64_t qos:3;
/*
* The group that the work queue entry will be
* scheduled to grp is used for CVMX_POW_TAG_OP_ADDWQ,
* CVMX_POW_TAG_OP_SWTAG_FULL,
* CVMX_POW_TAG_OP_SWTAG_DESCH, and
* CVMX_POW_TAG_OP_UPDATE_WQP_GRP
*/
uint64_t grp:4;
/*
* The type of the tag. type is used for everything
* except CVMX_POW_TAG_OP_DESCH,
* CVMX_POW_TAG_OP_UPDATE_WQP_GRP, and
* CVMX_POW_TAG_OP_*_NSCHED
*/
uint64_t type:3;
/*
* The actual tag. tag is used for everything except
* CVMX_POW_TAG_OP_DESCH,
* CVMX_POW_TAG_OP_UPDATE_WQP_GRP, and
* CVMX_POW_TAG_OP_*_NSCHED
*/
uint64_t tag:32;
} s;
} cvmx_pow_tag_req_t;
/**
* This structure describes the address to load stuff from POW
*/
typedef union {
uint64_t u64;
/**
* Address for new work request loads (did<2:0> == 0)
*/
struct {
/* Mips64 address region. Should be CVMX_IO_SEG */
uint64_t mem_region:2;
/* Must be zero */
uint64_t reserved_49_61:13;
/* Must be one */
uint64_t is_io:1;
/* the ID of POW -- did<2:0> == 0 in this case */
uint64_t did:8;
/* Must be zero */
uint64_t reserved_4_39:36;
/*
* If set, don't return load response until work is
* available.
*/
uint64_t wait:1;
/* Must be zero */
uint64_t reserved_0_2:3;
} swork;
/**
* Address for loads to get POW internal status
*/
struct {
/* Mips64 address region. Should be CVMX_IO_SEG */
uint64_t mem_region:2;
/* Must be zero */
uint64_t reserved_49_61:13;
/* Must be one */
uint64_t is_io:1;
/* the ID of POW -- did<2:0> == 1 in this case */
uint64_t did:8;
/* Must be zero */
uint64_t reserved_10_39:30;
/* The core id to get status for */
uint64_t coreid:4;
/*
* If set and get_cur is set, return reverse tag-list
* pointer rather than forward tag-list pointer.
*/
uint64_t get_rev:1;
/*
* If set, return current status rather than pending
* status.
*/
uint64_t get_cur:1;
/*
* If set, get the work-queue pointer rather than
* tag/type.
*/
uint64_t get_wqp:1;
/* Must be zero */
uint64_t reserved_0_2:3;
} sstatus;
/**
* Address for memory loads to get POW internal state
*/
struct {
/* Mips64 address region. Should be CVMX_IO_SEG */
uint64_t mem_region:2;
/* Must be zero */
uint64_t reserved_49_61:13;
/* Must be one */
uint64_t is_io:1;
/* the ID of POW -- did<2:0> == 2 in this case */
uint64_t did:8;
/* Must be zero */
uint64_t reserved_16_39:24;
/* POW memory index */
uint64_t index:11;
/*
* If set, return deschedule information rather than
* the standard response for work-queue index (invalid
* if the work-queue entry is not on the deschedule
* list).
*/
uint64_t get_des:1;
/*
* If set, get the work-queue pointer rather than
* tag/type (no effect when get_des set).
*/
uint64_t get_wqp:1;
/* Must be zero */
uint64_t reserved_0_2:3;
} smemload;
/**
* Address for index/pointer loads
*/
struct {
/* Mips64 address region. Should be CVMX_IO_SEG */
uint64_t mem_region:2;
/* Must be zero */
uint64_t reserved_49_61:13;
/* Must be one */
uint64_t is_io:1;
/* the ID of POW -- did<2:0> == 3 in this case */
uint64_t did:8;
/* Must be zero */
uint64_t reserved_9_39:31;
/*
* when {get_rmt ==0 AND get_des_get_tail == 0}, this
* field selects one of eight POW internal-input
* queues (0-7), one per QOS level; values 8-15 are
* illegal in this case; when {get_rmt ==0 AND
* get_des_get_tail == 1}, this field selects one of
* 16 deschedule lists (per group); when get_rmt ==1,
* this field selects one of 16 memory-input queue
* lists. The two memory-input queue lists associated
* with each QOS level are:
*
* - qosgrp = 0, qosgrp = 8: QOS0
* - qosgrp = 1, qosgrp = 9: QOS1
* - qosgrp = 2, qosgrp = 10: QOS2
* - qosgrp = 3, qosgrp = 11: QOS3
* - qosgrp = 4, qosgrp = 12: QOS4
* - qosgrp = 5, qosgrp = 13: QOS5
* - qosgrp = 6, qosgrp = 14: QOS6
* - qosgrp = 7, qosgrp = 15: QOS7
*/
uint64_t qosgrp:4;
/*
* If set and get_rmt is clear, return deschedule list
* indexes rather than indexes for the specified qos
* level; if set and get_rmt is set, return the tail
* pointer rather than the head pointer for the
* specified qos level.
*/
uint64_t get_des_get_tail:1;
/*
* If set, return remote pointers rather than the
* local indexes for the specified qos level.
*/
uint64_t get_rmt:1;
/* Must be zero */
uint64_t reserved_0_2:3;
} sindexload;
/**
* address for NULL_RD request (did<2:0> == 4) when this is read,
* HW attempts to change the state to NULL if it is NULL_NULL (the
* hardware cannot switch from NULL_NULL to NULL if a POW entry is
* not available - software may need to recover by finishing
* another piece of work before a POW entry can ever become
* available.)
*/
struct {
/* Mips64 address region. Should be CVMX_IO_SEG */
uint64_t mem_region:2;
/* Must be zero */
uint64_t reserved_49_61:13;
/* Must be one */
uint64_t is_io:1;
/* the ID of POW -- did<2:0> == 4 in this case */
uint64_t did:8;
/* Must be zero */
uint64_t reserved_0_39:40;
} snull_rd;
} cvmx_pow_load_addr_t;
/**
* This structure defines the response to a load/SENDSINGLE to POW
* (except CSR reads)
*/
typedef union {
uint64_t u64;
/**
* Response to new work request loads
*/
struct {
/*
* Set when no new work queue entry was returned. *
* If there was de-scheduled work, the HW will
* definitely return it. When this bit is set, it
* could mean either mean:
*
* - There was no work, or
*
* - There was no work that the HW could find. This
* case can happen, regardless of the wait bit value
* in the original request, when there is work in
* the IQ's that is too deep down the list.
*/
uint64_t no_work:1;
/* Must be zero */
uint64_t reserved_40_62:23;
/* 36 in O1 -- the work queue pointer */
uint64_t addr:40;
} s_work;
/**
* Result for a POW Status Load (when get_cur==0 and get_wqp==0)
*/
struct {
uint64_t reserved_62_63:2;
/* Set when there is a pending non-NULL SWTAG or
* SWTAG_FULL, and the POW entry has not left the list
* for the original tag. */
uint64_t pend_switch:1;
/* Set when SWTAG_FULL and pend_switch is set. */
uint64_t pend_switch_full:1;
/*
* Set when there is a pending NULL SWTAG, or an
* implicit switch to NULL.
*/
uint64_t pend_switch_null:1;
/* Set when there is a pending DESCHED or SWTAG_DESCHED. */
uint64_t pend_desched:1;
/*
* Set when there is a pending SWTAG_DESCHED and
* pend_desched is set.
*/
uint64_t pend_desched_switch:1;
/* Set when nosched is desired and pend_desched is set. */
uint64_t pend_nosched:1;
/* Set when there is a pending GET_WORK. */
uint64_t pend_new_work:1;
/*
* When pend_new_work is set, this bit indicates that
* the wait bit was set.
*/
uint64_t pend_new_work_wait:1;
/* Set when there is a pending NULL_RD. */
uint64_t pend_null_rd:1;
/* Set when there is a pending CLR_NSCHED. */
uint64_t pend_nosched_clr:1;
uint64_t reserved_51:1;
/* This is the index when pend_nosched_clr is set. */
uint64_t pend_index:11;
/*
* This is the new_grp when (pend_desched AND
* pend_desched_switch) is set.
*/
uint64_t pend_grp:4;
uint64_t reserved_34_35:2;
/*
* This is the tag type when pend_switch or
* (pend_desched AND pend_desched_switch) are set.
*/
uint64_t pend_type:2;
/*
* - this is the tag when pend_switch or (pend_desched
* AND pend_desched_switch) are set.
*/
uint64_t pend_tag:32;
} s_sstatus0;
/**
* Result for a POW Status Load (when get_cur==0 and get_wqp==1)
*/
struct {
uint64_t reserved_62_63:2;
/*
* Set when there is a pending non-NULL SWTAG or
* SWTAG_FULL, and the POW entry has not left the list
* for the original tag.
*/
uint64_t pend_switch:1;
/* Set when SWTAG_FULL and pend_switch is set. */
uint64_t pend_switch_full:1;
/*
* Set when there is a pending NULL SWTAG, or an
* implicit switch to NULL.
*/
uint64_t pend_switch_null:1;
/*
* Set when there is a pending DESCHED or
* SWTAG_DESCHED.
*/
uint64_t pend_desched:1;
/*
* Set when there is a pending SWTAG_DESCHED and
* pend_desched is set.
*/
uint64_t pend_desched_switch:1;
/* Set when nosched is desired and pend_desched is set. */
uint64_t pend_nosched:1;
/* Set when there is a pending GET_WORK. */
uint64_t pend_new_work:1;
/*
* When pend_new_work is set, this bit indicates that
* the wait bit was set.
*/
uint64_t pend_new_work_wait:1;
/* Set when there is a pending NULL_RD. */
uint64_t pend_null_rd:1;
/* Set when there is a pending CLR_NSCHED. */
uint64_t pend_nosched_clr:1;
uint64_t reserved_51:1;
/* This is the index when pend_nosched_clr is set. */
uint64_t pend_index:11;
/*
* This is the new_grp when (pend_desched AND
* pend_desched_switch) is set.
*/
uint64_t pend_grp:4;
/* This is the wqp when pend_nosched_clr is set. */
uint64_t pend_wqp:36;
} s_sstatus1;
/**
* Result for a POW Status Load (when get_cur==1, get_wqp==0, and
* get_rev==0)
*/
struct {
uint64_t reserved_62_63:2;
/*
* Points to the next POW entry in the tag list when
* tail == 0 (and tag_type is not NULL or NULL_NULL).
*/
uint64_t link_index:11;
/* The POW entry attached to the core. */
uint64_t index:11;
/*
* The group attached to the core (updated when new
* tag list entered on SWTAG_FULL).
*/
uint64_t grp:4;
/*
* Set when this POW entry is at the head of its tag
* list (also set when in the NULL or NULL_NULL
* state).
*/
uint64_t head:1;
/*
* Set when this POW entry is at the tail of its tag
* list (also set when in the NULL or NULL_NULL
* state).
*/
uint64_t tail:1;
/*
* The tag type attached to the core (updated when new
* tag list entered on SWTAG, SWTAG_FULL, or
* SWTAG_DESCHED).
*/
uint64_t tag_type:2;
/*
* The tag attached to the core (updated when new tag
* list entered on SWTAG, SWTAG_FULL, or
* SWTAG_DESCHED).
*/
uint64_t tag:32;
} s_sstatus2;
/**
* Result for a POW Status Load (when get_cur==1, get_wqp==0, and get_rev==1)
*/
struct {
uint64_t reserved_62_63:2;
/*
* Points to the prior POW entry in the tag list when
* head == 0 (and tag_type is not NULL or
* NULL_NULL). This field is unpredictable when the
* core's state is NULL or NULL_NULL.
*/
uint64_t revlink_index:11;
/* The POW entry attached to the core. */
uint64_t index:11;
/*
* The group attached to the core (updated when new
* tag list entered on SWTAG_FULL).
*/
uint64_t grp:4;
/* Set when this POW entry is at the head of its tag
* list (also set when in the NULL or NULL_NULL
* state).
*/
uint64_t head:1;
/*
* Set when this POW entry is at the tail of its tag
* list (also set when in the NULL or NULL_NULL
* state).
*/
uint64_t tail:1;
/*
* The tag type attached to the core (updated when new
* tag list entered on SWTAG, SWTAG_FULL, or
* SWTAG_DESCHED).
*/
uint64_t tag_type:2;
/*
* The tag attached to the core (updated when new tag
* list entered on SWTAG, SWTAG_FULL, or
* SWTAG_DESCHED).
*/
uint64_t tag:32;
} s_sstatus3;
/**
* Result for a POW Status Load (when get_cur==1, get_wqp==1, and
* get_rev==0)
*/
struct {
uint64_t reserved_62_63:2;
/*
* Points to the next POW entry in the tag list when
* tail == 0 (and tag_type is not NULL or NULL_NULL).
*/
uint64_t link_index:11;
/* The POW entry attached to the core. */
uint64_t index:11;
/*
* The group attached to the core (updated when new
* tag list entered on SWTAG_FULL).
*/
uint64_t grp:4;
/*
* The wqp attached to the core (updated when new tag
* list entered on SWTAG_FULL).
*/
uint64_t wqp:36;
} s_sstatus4;
/**
* Result for a POW Status Load (when get_cur==1, get_wqp==1, and
* get_rev==1)
*/
struct {
uint64_t reserved_62_63:2;
/*
* Points to the prior POW entry in the tag list when
* head == 0 (and tag_type is not NULL or
* NULL_NULL). This field is unpredictable when the
* core's state is NULL or NULL_NULL.
*/
uint64_t revlink_index:11;
/* The POW entry attached to the core. */
uint64_t index:11;
/*
* The group attached to the core (updated when new
* tag list entered on SWTAG_FULL).
*/
uint64_t grp:4;
/*
* The wqp attached to the core (updated when new tag
* list entered on SWTAG_FULL).
*/
uint64_t wqp:36;
} s_sstatus5;
/**
* Result For POW Memory Load (get_des == 0 and get_wqp == 0)
*/
struct {
uint64_t reserved_51_63:13;
/*
* The next entry in the input, free, descheduled_head
* list (unpredictable if entry is the tail of the
* list).
*/
uint64_t next_index:11;
/* The group of the POW entry. */
uint64_t grp:4;
uint64_t reserved_35:1;
/*
* Set when this POW entry is at the tail of its tag
* list (also set when in the NULL or NULL_NULL
* state).
*/
uint64_t tail:1;
/* The tag type of the POW entry. */
uint64_t tag_type:2;
/* The tag of the POW entry. */
uint64_t tag:32;
} s_smemload0;
/**
* Result For POW Memory Load (get_des == 0 and get_wqp == 1)
*/
struct {
uint64_t reserved_51_63:13;
/*
* The next entry in the input, free, descheduled_head
* list (unpredictable if entry is the tail of the
* list).
*/
uint64_t next_index:11;
/* The group of the POW entry. */
uint64_t grp:4;
/* The WQP held in the POW entry. */
uint64_t wqp:36;
} s_smemload1;
/**
* Result For POW Memory Load (get_des == 1)
*/
struct {
uint64_t reserved_51_63:13;
/*
* The next entry in the tag list connected to the
* descheduled head.
*/
uint64_t fwd_index:11;
/* The group of the POW entry. */
uint64_t grp:4;
/* The nosched bit for the POW entry. */
uint64_t nosched:1;
/* There is a pending tag switch */
uint64_t pend_switch:1;
/*
* The next tag type for the new tag list when
* pend_switch is set.
*/
uint64_t pend_type:2;
/*
* The next tag for the new tag list when pend_switch
* is set.
*/
uint64_t pend_tag:32;
} s_smemload2;
/**
* Result For POW Index/Pointer Load (get_rmt == 0/get_des_get_tail == 0)
*/
struct {
uint64_t reserved_52_63:12;
/*
* set when there is one or more POW entries on the
* free list.
*/
uint64_t free_val:1;
/*
* set when there is exactly one POW entry on the free
* list.
*/
uint64_t free_one:1;
uint64_t reserved_49:1;
/*
* when free_val is set, indicates the first entry on
* the free list.
*/
uint64_t free_head:11;
uint64_t reserved_37:1;
/*
* when free_val is set, indicates the last entry on
* the free list.
*/
uint64_t free_tail:11;
/*
* set when there is one or more POW entries on the
* input Q list selected by qosgrp.
*/
uint64_t loc_val:1;
/*
* set when there is exactly one POW entry on the
* input Q list selected by qosgrp.
*/
uint64_t loc_one:1;
uint64_t reserved_23:1;
/*
* when loc_val is set, indicates the first entry on
* the input Q list selected by qosgrp.
*/
uint64_t loc_head:11;
uint64_t reserved_11:1;
/*
* when loc_val is set, indicates the last entry on
* the input Q list selected by qosgrp.
*/
uint64_t loc_tail:11;
} sindexload0;
/**
* Result For POW Index/Pointer Load (get_rmt == 0/get_des_get_tail == 1)
*/
struct {
uint64_t reserved_52_63:12;
/*
* set when there is one or more POW entries on the
* nosched list.
*/
uint64_t nosched_val:1;
/*
* set when there is exactly one POW entry on the
* nosched list.
*/
uint64_t nosched_one:1;
uint64_t reserved_49:1;
/*
* when nosched_val is set, indicates the first entry
* on the nosched list.
*/
uint64_t nosched_head:11;
uint64_t reserved_37:1;
/*
* when nosched_val is set, indicates the last entry
* on the nosched list.
*/
uint64_t nosched_tail:11;
/*
* set when there is one or more descheduled heads on
* the descheduled list selected by qosgrp.
*/
uint64_t des_val:1;
/*
* set when there is exactly one descheduled head on
* the descheduled list selected by qosgrp.
*/
uint64_t des_one:1;
uint64_t reserved_23:1;
/*
* when des_val is set, indicates the first
* descheduled head on the descheduled list selected
* by qosgrp.
*/
uint64_t des_head:11;
uint64_t reserved_11:1;
/*
* when des_val is set, indicates the last descheduled
* head on the descheduled list selected by qosgrp.
*/
uint64_t des_tail:11;
} sindexload1;
/**
* Result For POW Index/Pointer Load (get_rmt == 1/get_des_get_tail == 0)
*/
struct {
uint64_t reserved_39_63:25;
/*
* Set when this DRAM list is the current head
* (i.e. is the next to be reloaded when the POW
* hardware reloads a POW entry from DRAM). The POW
* hardware alternates between the two DRAM lists
* associated with a QOS level when it reloads work
* from DRAM into the POW unit.
*/
uint64_t rmt_is_head:1;
/*
* Set when the DRAM portion of the input Q list
* selected by qosgrp contains one or more pieces of
* work.
*/
uint64_t rmt_val:1;
/*
* Set when the DRAM portion of the input Q list
* selected by qosgrp contains exactly one piece of
* work.
*/
uint64_t rmt_one:1;
/*
* When rmt_val is set, indicates the first piece of
* work on the DRAM input Q list selected by
* qosgrp.
*/
uint64_t rmt_head:36;
} sindexload2;
/**
* Result For POW Index/Pointer Load (get_rmt ==
* 1/get_des_get_tail == 1)
*/
struct {
uint64_t reserved_39_63:25;
/*
* set when this DRAM list is the current head
* (i.e. is the next to be reloaded when the POW
* hardware reloads a POW entry from DRAM). The POW
* hardware alternates between the two DRAM lists
* associated with a QOS level when it reloads work
* from DRAM into the POW unit.
*/
uint64_t rmt_is_head:1;
/*
* set when the DRAM portion of the input Q list
* selected by qosgrp contains one or more pieces of
* work.
*/
uint64_t rmt_val:1;
/*
* set when the DRAM portion of the input Q list
* selected by qosgrp contains exactly one piece of
* work.
*/
uint64_t rmt_one:1;
/*
* when rmt_val is set, indicates the last piece of
* work on the DRAM input Q list selected by
* qosgrp.
*/
uint64_t rmt_tail:36;
} sindexload3;
/**
* Response to NULL_RD request loads
*/
struct {
uint64_t unused:62;
/* of type cvmx_pow_tag_type_t. state is one of the
* following:
*
* - CVMX_POW_TAG_TYPE_ORDERED
* - CVMX_POW_TAG_TYPE_ATOMIC
* - CVMX_POW_TAG_TYPE_NULL
* - CVMX_POW_TAG_TYPE_NULL_NULL
*/
uint64_t state:2;
} s_null_rd;
} cvmx_pow_tag_load_resp_t;
/**
* This structure describes the address used for stores to the POW.
* The store address is meaningful on stores to the POW. The
* hardware assumes that an aligned 64-bit store was used for all
* these stores. Note the assumption that the work queue entry is
* aligned on an 8-byte boundary (since the low-order 3 address bits
* must be zero). Note that not all fields are used by all
* operations.
*
* NOTE: The following is the behavior of the pending switch bit at the PP
* for POW stores (i.e. when did<7:3> == 0xc)
* - did<2:0> == 0 => pending switch bit is set
* - did<2:0> == 1 => no affect on the pending switch bit
* - did<2:0> == 3 => pending switch bit is cleared
* - did<2:0> == 7 => no affect on the pending switch bit
* - did<2:0> == others => must not be used
* - No other loads/stores have an affect on the pending switch bit
* - The switch bus from POW can clear the pending switch bit
*
* NOTE: did<2:0> == 2 is used by the HW for a special single-cycle
* ADDWQ command that only contains the pointer). SW must never use
* did<2:0> == 2.
*/
typedef union {
/**
* Unsigned 64 bit integer representation of store address
*/
uint64_t u64;
struct {
/* Memory region. Should be CVMX_IO_SEG in most cases */
uint64_t mem_reg:2;
uint64_t reserved_49_61:13; /* Must be zero */
uint64_t is_io:1; /* Must be one */
/* Device ID of POW. Note that different sub-dids are used. */
uint64_t did:8;
uint64_t reserved_36_39:4; /* Must be zero */
/* Address field. addr<2:0> must be zero */
uint64_t addr:36;
} stag;
} cvmx_pow_tag_store_addr_t;
/**
* decode of the store data when an IOBDMA SENDSINGLE is sent to POW
*/
typedef union {
uint64_t u64;
struct {
/*
* the (64-bit word) location in scratchpad to write
* to (if len != 0)
*/
uint64_t scraddr:8;
/* the number of words in the response (0 => no response) */
uint64_t len:8;
/* the ID of the device on the non-coherent bus */
uint64_t did:8;
uint64_t unused:36;
/* if set, don't return load response until work is available */
uint64_t wait:1;
uint64_t unused2:3;
} s;
} cvmx_pow_iobdma_store_t;