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@mamedev @YosysHQ

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12 stars written in Verilog
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FPGA implementation of DEC PDP-1 computer (1959) in Verilog, with CRT, Teletype and Console.

Verilog 188 16 Updated Jul 9, 2022

LunaPnR is a place and router for integrated circuits

Verilog 41 1 Updated Jul 25, 2024

AGM bitstream utilities and decoded files from Supra

Verilog 39 12 Updated Mar 26, 2024

An FPGA/PCI Device Reference Platform

Verilog 29 3 Updated Dec 10, 2020

HiLoTOF -- Hardware-in-the-Loop Test framework for Open FPGAs

Verilog 12 3 Updated Feb 9, 2019

Picorv32 SoC that uses only BRAM, not flash memory

Verilog 12 4 Updated Nov 27, 2018

Löwe FPGA Board

Verilog 12 1 Updated Oct 12, 2023

Minimal ZX Spectrum for Ulx3s ECP5 board

Verilog 11 5 Updated May 7, 2020
Verilog 6 Updated May 17, 2023

Third-party bitstream documentation for Altera MAX7000 CPLDs

Verilog 5 Updated Jul 12, 2024

a simple Z80 Soc for ULX3S (ECP5 FPGA)

Verilog 4 Updated Dec 2, 2019

My projects for ULX3S FPGA

Verilog 2 Updated Feb 27, 2019