From d1019a74e0f562c3c60d1bdcf73048bea0f1cb24 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Thomas=20Wei=C3=9Fschuh?= Date: Fri, 24 May 2024 10:33:33 +0200 Subject: [PATCH 01/28] platform/chrome: cros_ec_proto: Fix cros_ec_get_host_event_wake_mask kdoc MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Mark the documentation block as kernel doc and drop the documentation of the non-existing parameter "@msg". Signed-off-by: Thomas Weißschuh Link: https://lore.kernel.org/r/20240524-cros_ec-cmd_versions-v1-1-8a148647d051@weissschuh.net Signed-off-by: Tzung-Bi Shih --- drivers/platform/chrome/cros_ec_proto.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/platform/chrome/cros_ec_proto.c b/drivers/platform/chrome/cros_ec_proto.c index 945b1b15a04cae..0006a343964499 100644 --- a/drivers/platform/chrome/cros_ec_proto.c +++ b/drivers/platform/chrome/cros_ec_proto.c @@ -239,13 +239,12 @@ int cros_ec_check_result(struct cros_ec_device *ec_dev, } EXPORT_SYMBOL(cros_ec_check_result); -/* +/** * cros_ec_get_host_event_wake_mask * * Get the mask of host events that cause wake from suspend. * * @ec_dev: EC device to call - * @msg: message structure to use * @mask: result when function returns 0. * * LOCKING: From c48a71a8877241e44cdc84f479ed57a9c1c62c15 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Thomas=20Wei=C3=9Fschuh?= Date: Fri, 24 May 2024 10:33:34 +0200 Subject: [PATCH 02/28] platform/chrome: cros_ec_proto: Fix cros_ec_get_host_command_version_mask kdoc MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Mark the documentation block as kernel doc and drop the documentation of the non-existing parameter "@msg". Signed-off-by: Thomas Weißschuh Link: https://lore.kernel.org/r/20240524-cros_ec-cmd_versions-v1-2-8a148647d051@weissschuh.net Signed-off-by: Tzung-Bi Shih --- drivers/platform/chrome/cros_ec_proto.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/platform/chrome/cros_ec_proto.c b/drivers/platform/chrome/cros_ec_proto.c index 0006a343964499..dcfc18fe1cdf78 100644 --- a/drivers/platform/chrome/cros_ec_proto.c +++ b/drivers/platform/chrome/cros_ec_proto.c @@ -426,13 +426,12 @@ static int cros_ec_get_proto_info_legacy(struct cros_ec_device *ec_dev) return ret; } -/* +/** * cros_ec_get_host_command_version_mask * * Get the version mask of a given command. * * @ec_dev: EC device to call - * @msg: message structure to use * @cmd: command to get the version of. * @mask: result when function returns 0. * From 47ef58cdbd7fae42f1adcb6015fdc05ce2b2471e Mon Sep 17 00:00:00 2001 From: Tzung-Bi Shih Date: Tue, 30 Apr 2024 10:09:24 +0800 Subject: [PATCH 03/28] platform/chrome: cros_ec: let cros_ec_suspend() call cros_ec_suspend_* After commit 2fbe479c0024 ("platform/chrome: cros_ec: Handle events during suspend after resume completion"), cros_ec_resume() starts to call cros_ec_resume_early() and cros_ec_resume_complete(). To be neat, let cros_ec_suspend() call cros_ec_suspend_prepare() and cros_ec_suspend_late(). Reviewed-by: Prashant Malani Link: https://lore.kernel.org/r/20240430020924.610724-1-tzungbi@kernel.org Signed-off-by: Tzung-Bi Shih --- drivers/platform/chrome/cros_ec.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/platform/chrome/cros_ec.c b/drivers/platform/chrome/cros_ec.c index 47d19f7e295a7a..e821b3d3959094 100644 --- a/drivers/platform/chrome/cros_ec.c +++ b/drivers/platform/chrome/cros_ec.c @@ -388,8 +388,8 @@ EXPORT_SYMBOL(cros_ec_suspend_late); */ int cros_ec_suspend(struct cros_ec_device *ec_dev) { - cros_ec_send_suspend_event(ec_dev); - cros_ec_disable_irq(ec_dev); + cros_ec_suspend_prepare(ec_dev); + cros_ec_suspend_late(ec_dev); return 0; } EXPORT_SYMBOL(cros_ec_suspend); From 7b44d5381e541de3da3cee2e948456b250f41f25 Mon Sep 17 00:00:00 2001 From: Rob Barnes Date: Tue, 7 May 2024 15:58:09 +0000 Subject: [PATCH 04/28] platform/chrome: cros_ec_debugfs: Make log polling period a parameter Make EC log polling period a module parameter. This allows the polling period to be set via the kernel command line. Keeping the default at the current 10 second period. The optimal polling period will differ by board. Signed-off-by: Rob Barnes Link: https://lore.kernel.org/r/20240507155809.525701-1-robbarnes@google.com Signed-off-by: Tzung-Bi Shih --- drivers/platform/chrome/cros_ec_debugfs.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/platform/chrome/cros_ec_debugfs.c b/drivers/platform/chrome/cros_ec_debugfs.c index e1d313246beb5a..f0e9efb543df6c 100644 --- a/drivers/platform/chrome/cros_ec_debugfs.c +++ b/drivers/platform/chrome/cros_ec_debugfs.c @@ -26,6 +26,10 @@ #define CIRC_ADD(idx, size, value) (((idx) + (value)) & ((size) - 1)) +static unsigned int log_poll_period_ms = LOG_POLL_SEC * MSEC_PER_SEC; +module_param(log_poll_period_ms, uint, 0644); +MODULE_PARM_DESC(log_poll_period_ms, "EC log polling period(ms)"); + /* waitqueue for log readers */ static DECLARE_WAIT_QUEUE_HEAD(cros_ec_debugfs_log_wq); @@ -57,7 +61,7 @@ struct cros_ec_debugfs { /* * We need to make sure that the EC log buffer on the UART is large enough, - * so that it is unlikely enough to overlow within LOG_POLL_SEC. + * so that it is unlikely enough to overlow within log_poll_period_ms. */ static void cros_ec_console_log_work(struct work_struct *__work) { @@ -119,7 +123,7 @@ static void cros_ec_console_log_work(struct work_struct *__work) resched: schedule_delayed_work(&debug_info->log_poll_work, - msecs_to_jiffies(LOG_POLL_SEC * 1000)); + msecs_to_jiffies(log_poll_period_ms)); } static int cros_ec_console_log_open(struct inode *inode, struct file *file) From a14a569a9918a0c7e340257a17dbc088bb27db72 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Thomas=20Wei=C3=9Fschuh?= Date: Wed, 29 May 2024 08:27:11 +0200 Subject: [PATCH 05/28] platform/chrome: cros_ec_proto: Introduce cros_ec_cmd_readmem() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit To read from the EC memory different mechanism are possible. ECs connected via LPC expose their memory via a ->cmd_readmem operation. Other protocols require the usage of EC_CMD_READ_MEMMAP, which on the other hand is not implemented by LPC ECs. Provide a helper that automatically selects the correct mechanism. Signed-off-by: Thomas Weißschuh Reviewed-by: Guenter Roeck Link: https://lore.kernel.org/r/20240529-cros_ec-hwmon-v4-1-5cdf0c5db50a@weissschuh.net Signed-off-by: Tzung-Bi Shih --- drivers/platform/chrome/cros_ec_proto.c | 27 +++++++++++++++++++++ include/linux/platform_data/cros_ec_proto.h | 2 ++ 2 files changed, 29 insertions(+) diff --git a/drivers/platform/chrome/cros_ec_proto.c b/drivers/platform/chrome/cros_ec_proto.c index dcfc18fe1cdf78..2ad1b8221ec0dc 100644 --- a/drivers/platform/chrome/cros_ec_proto.c +++ b/drivers/platform/chrome/cros_ec_proto.c @@ -1033,3 +1033,30 @@ int cros_ec_cmd(struct cros_ec_device *ec_dev, return ret; } EXPORT_SYMBOL_GPL(cros_ec_cmd); + +/** + * cros_ec_cmd_readmem - Read from EC memory. + * + * @ec_dev: EC device + * @offset: Is within EC_LPC_ADDR_MEMMAP region. + * @size: Number of bytes to read. + * @dest: EC command output data + * + * Return: >= 0 on success, negative error number on failure. + */ +int cros_ec_cmd_readmem(struct cros_ec_device *ec_dev, u8 offset, u8 size, void *dest) +{ + struct ec_params_read_memmap params = {}; + + if (!size) + return -EINVAL; + + if (ec_dev->cmd_readmem) + return ec_dev->cmd_readmem(ec_dev, offset, size, dest); + + params.offset = offset; + params.size = size; + return cros_ec_cmd(ec_dev, 0, EC_CMD_READ_MEMMAP, + ¶ms, sizeof(params), dest, size); +} +EXPORT_SYMBOL_GPL(cros_ec_cmd_readmem); diff --git a/include/linux/platform_data/cros_ec_proto.h b/include/linux/platform_data/cros_ec_proto.h index 8865e350c12a5f..1ddc52603f9ae2 100644 --- a/include/linux/platform_data/cros_ec_proto.h +++ b/include/linux/platform_data/cros_ec_proto.h @@ -261,6 +261,8 @@ int cros_ec_get_sensor_count(struct cros_ec_dev *ec); int cros_ec_cmd(struct cros_ec_device *ec_dev, unsigned int version, int command, const void *outdata, size_t outsize, void *indata, size_t insize); +int cros_ec_cmd_readmem(struct cros_ec_device *ec_dev, u8 offset, u8 size, void *dest); + /** * cros_ec_get_time_ns() - Return time in ns. * From bc3e45258096f2ea2116302abefde4b1cb9bc3c1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Thomas=20Wei=C3=9Fschuh?= Date: Wed, 29 May 2024 08:27:12 +0200 Subject: [PATCH 06/28] hwmon: add ChromeOS EC driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The ChromeOS Embedded Controller exposes fan speed and temperature readings. Expose this data through the hwmon subsystem. The driver is designed to be probed via the cros_ec mfd device. Signed-off-by: Thomas Weißschuh Acked-by: Guenter Roeck Link: https://lore.kernel.org/r/20240529-cros_ec-hwmon-v4-2-5cdf0c5db50a@weissschuh.net [tzungbi: Fixed typo in MAINTAINERS: "chros_ec_hwmon" -> "cros_ec_hwmon"] Signed-off-by: Tzung-Bi Shih --- Documentation/hwmon/cros_ec_hwmon.rst | 26 +++ Documentation/hwmon/index.rst | 1 + MAINTAINERS | 8 + drivers/hwmon/Kconfig | 11 + drivers/hwmon/Makefile | 1 + drivers/hwmon/cros_ec_hwmon.c | 282 ++++++++++++++++++++++++++ 6 files changed, 329 insertions(+) create mode 100644 Documentation/hwmon/cros_ec_hwmon.rst create mode 100644 drivers/hwmon/cros_ec_hwmon.c diff --git a/Documentation/hwmon/cros_ec_hwmon.rst b/Documentation/hwmon/cros_ec_hwmon.rst new file mode 100644 index 00000000000000..47ecae983bdbef --- /dev/null +++ b/Documentation/hwmon/cros_ec_hwmon.rst @@ -0,0 +1,26 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later + +Kernel driver cros_ec_hwmon +=========================== + +Supported chips: + + * ChromeOS embedded controllers. + + Prefix: 'cros_ec' + + Addresses scanned: - + +Author: + + - Thomas Weißschuh + +Description +----------- + +This driver implements support for hardware monitoring commands exposed by the +ChromeOS embedded controller used in Chromebooks and other devices. + +The channel labels exposed via hwmon are retrieved from the EC itself. + +Fan and temperature readings are supported. diff --git a/Documentation/hwmon/index.rst b/Documentation/hwmon/index.rst index 03d313af469a18..342ea5deba24fc 100644 --- a/Documentation/hwmon/index.rst +++ b/Documentation/hwmon/index.rst @@ -58,6 +58,7 @@ Hardware Monitoring Kernel Drivers coretemp corsair-cpro corsair-psu + cros_ec_hwmon da9052 da9055 dell-smm-hwmon diff --git a/MAINTAINERS b/MAINTAINERS index d6c90161c7bfe3..e4e6aad46668b5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -5135,6 +5135,14 @@ S: Maintained F: Documentation/devicetree/bindings/sound/google,cros-ec-codec.yaml F: sound/soc/codecs/cros_ec_codec.* +CHROMEOS EC HARDWARE MONITORING +M: Thomas Weißschuh +L: chrome-platform@lists.linux.dev +L: linux-hwmon@vger.kernel.org +S: Maintained +F: Documentation/hwmon/cros_ec_hwmon.rst +F: drivers/hwmon/cros_ec_hwmon.c + CHROMEOS EC SUBDRIVERS M: Benson Leung R: Guenter Roeck diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig index e14ae18a973b3c..702dc45ea40572 100644 --- a/drivers/hwmon/Kconfig +++ b/drivers/hwmon/Kconfig @@ -506,6 +506,17 @@ config SENSORS_CORSAIR_PSU This driver can also be built as a module. If so, the module will be called corsair-psu. +config SENSORS_CROS_EC + tristate "ChromeOS Embedded Controller sensors" + depends on MFD_CROS_EC_DEV + default MFD_CROS_EC_DEV + help + If you say yes here you get support for ChromeOS Embedded Controller + sensors. + + This driver can also be built as a module. If so, the module + will be called cros_ec_hwmon. + config SENSORS_DRIVETEMP tristate "Hard disk drives with temperature sensors" depends on SCSI && ATA diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile index e3f25475d1f043..4fb14dd1eafdfa 100644 --- a/drivers/hwmon/Makefile +++ b/drivers/hwmon/Makefile @@ -64,6 +64,7 @@ obj-$(CONFIG_SENSORS_CHIPCAP2) += chipcap2.o obj-$(CONFIG_SENSORS_CORETEMP) += coretemp.o obj-$(CONFIG_SENSORS_CORSAIR_CPRO) += corsair-cpro.o obj-$(CONFIG_SENSORS_CORSAIR_PSU) += corsair-psu.o +obj-$(CONFIG_SENSORS_CROS_EC) += cros_ec_hwmon.o obj-$(CONFIG_SENSORS_DA9052_ADC)+= da9052-hwmon.o obj-$(CONFIG_SENSORS_DA9055)+= da9055-hwmon.o obj-$(CONFIG_SENSORS_DELL_SMM) += dell-smm-hwmon.o diff --git a/drivers/hwmon/cros_ec_hwmon.c b/drivers/hwmon/cros_ec_hwmon.c new file mode 100644 index 00000000000000..41f268fa826098 --- /dev/null +++ b/drivers/hwmon/cros_ec_hwmon.c @@ -0,0 +1,282 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * ChromeOS EC driver for hwmon + * + * Copyright (C) 2024 Thomas Weißschuh + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DRV_NAME "cros-ec-hwmon" + +struct cros_ec_hwmon_priv { + struct cros_ec_device *cros_ec; + const char *temp_sensor_names[EC_TEMP_SENSOR_ENTRIES + EC_TEMP_SENSOR_B_ENTRIES]; + u8 usable_fans; +}; + +static int cros_ec_hwmon_read_fan_speed(struct cros_ec_device *cros_ec, u8 index, u16 *speed) +{ + int ret; + + ret = cros_ec_cmd_readmem(cros_ec, EC_MEMMAP_FAN + index * 2, 2, speed); + if (ret < 0) + return ret; + + *speed = le16_to_cpu(*speed); + return 0; +} + +static int cros_ec_hwmon_read_temp(struct cros_ec_device *cros_ec, u8 index, u8 *temp) +{ + unsigned int offset; + int ret; + + if (index < EC_TEMP_SENSOR_ENTRIES) + offset = EC_MEMMAP_TEMP_SENSOR + index; + else + offset = EC_MEMMAP_TEMP_SENSOR_B + index - EC_TEMP_SENSOR_ENTRIES; + + ret = cros_ec_cmd_readmem(cros_ec, offset, 1, temp); + if (ret < 0) + return ret; + return 0; +} + +static bool cros_ec_hwmon_is_error_fan(u16 speed) +{ + return speed == EC_FAN_SPEED_NOT_PRESENT || speed == EC_FAN_SPEED_STALLED; +} + +static bool cros_ec_hwmon_is_error_temp(u8 temp) +{ + return temp == EC_TEMP_SENSOR_NOT_PRESENT || + temp == EC_TEMP_SENSOR_ERROR || + temp == EC_TEMP_SENSOR_NOT_POWERED || + temp == EC_TEMP_SENSOR_NOT_CALIBRATED; +} + +static long cros_ec_hwmon_temp_to_millicelsius(u8 temp) +{ + return kelvin_to_millicelsius((((long)temp) + EC_TEMP_SENSOR_OFFSET)); +} + +static int cros_ec_hwmon_read(struct device *dev, enum hwmon_sensor_types type, + u32 attr, int channel, long *val) +{ + struct cros_ec_hwmon_priv *priv = dev_get_drvdata(dev); + int ret = -EOPNOTSUPP; + u16 speed; + u8 temp; + + if (type == hwmon_fan) { + if (attr == hwmon_fan_input) { + ret = cros_ec_hwmon_read_fan_speed(priv->cros_ec, channel, &speed); + if (ret == 0) { + if (cros_ec_hwmon_is_error_fan(speed)) + ret = -ENODATA; + else + *val = speed; + } + } else if (attr == hwmon_fan_fault) { + ret = cros_ec_hwmon_read_fan_speed(priv->cros_ec, channel, &speed); + if (ret == 0) + *val = cros_ec_hwmon_is_error_fan(speed); + } + } else if (type == hwmon_temp) { + if (attr == hwmon_temp_input) { + ret = cros_ec_hwmon_read_temp(priv->cros_ec, channel, &temp); + if (ret == 0) { + if (cros_ec_hwmon_is_error_temp(temp)) + ret = -ENODATA; + else + *val = cros_ec_hwmon_temp_to_millicelsius(temp); + } + } else if (attr == hwmon_temp_fault) { + ret = cros_ec_hwmon_read_temp(priv->cros_ec, channel, &temp); + if (ret == 0) + *val = cros_ec_hwmon_is_error_temp(temp); + } + } + + return ret; +} + +static int cros_ec_hwmon_read_string(struct device *dev, enum hwmon_sensor_types type, + u32 attr, int channel, const char **str) +{ + struct cros_ec_hwmon_priv *priv = dev_get_drvdata(dev); + + if (type == hwmon_temp && attr == hwmon_temp_label) { + *str = priv->temp_sensor_names[channel]; + return 0; + } + + return -EOPNOTSUPP; +} + +static umode_t cros_ec_hwmon_is_visible(const void *data, enum hwmon_sensor_types type, + u32 attr, int channel) +{ + const struct cros_ec_hwmon_priv *priv = data; + + if (type == hwmon_fan) { + if (priv->usable_fans & BIT(channel)) + return 0444; + } else if (type == hwmon_temp) { + if (priv->temp_sensor_names[channel]) + return 0444; + } + + return 0; +} + +static const struct hwmon_channel_info * const cros_ec_hwmon_info[] = { + HWMON_CHANNEL_INFO(fan, + HWMON_F_INPUT | HWMON_F_FAULT, + HWMON_F_INPUT | HWMON_F_FAULT, + HWMON_F_INPUT | HWMON_F_FAULT, + HWMON_F_INPUT | HWMON_F_FAULT), + HWMON_CHANNEL_INFO(temp, + HWMON_T_INPUT | HWMON_T_FAULT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_FAULT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_FAULT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_FAULT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_FAULT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_FAULT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_FAULT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_FAULT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_FAULT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_FAULT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_FAULT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_FAULT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_FAULT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_FAULT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_FAULT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_FAULT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_FAULT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_FAULT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_FAULT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_FAULT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_FAULT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_FAULT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_FAULT | HWMON_T_LABEL, + HWMON_T_INPUT | HWMON_T_FAULT | HWMON_T_LABEL), + NULL +}; + +static const struct hwmon_ops cros_ec_hwmon_ops = { + .read = cros_ec_hwmon_read, + .read_string = cros_ec_hwmon_read_string, + .is_visible = cros_ec_hwmon_is_visible, +}; + +static const struct hwmon_chip_info cros_ec_hwmon_chip_info = { + .ops = &cros_ec_hwmon_ops, + .info = cros_ec_hwmon_info, +}; + +static void cros_ec_hwmon_probe_temp_sensors(struct device *dev, struct cros_ec_hwmon_priv *priv, + u8 thermal_version) +{ + struct ec_params_temp_sensor_get_info req = {}; + struct ec_response_temp_sensor_get_info resp; + size_t candidates, i, sensor_name_size; + int ret; + u8 temp; + + if (thermal_version < 2) + candidates = EC_TEMP_SENSOR_ENTRIES; + else + candidates = ARRAY_SIZE(priv->temp_sensor_names); + + for (i = 0; i < candidates; i++) { + if (cros_ec_hwmon_read_temp(priv->cros_ec, i, &temp) < 0) + continue; + + if (temp == EC_TEMP_SENSOR_NOT_PRESENT) + continue; + + req.id = i; + ret = cros_ec_cmd(priv->cros_ec, 0, EC_CMD_TEMP_SENSOR_GET_INFO, + &req, sizeof(req), &resp, sizeof(resp)); + if (ret < 0) + continue; + + sensor_name_size = strnlen(resp.sensor_name, sizeof(resp.sensor_name)); + priv->temp_sensor_names[i] = devm_kasprintf(dev, GFP_KERNEL, "%*s", + (int)sensor_name_size, + resp.sensor_name); + } +} + +static void cros_ec_hwmon_probe_fans(struct cros_ec_hwmon_priv *priv) +{ + u16 speed; + size_t i; + int ret; + + for (i = 0; i < EC_FAN_SPEED_ENTRIES; i++) { + ret = cros_ec_hwmon_read_fan_speed(priv->cros_ec, i, &speed); + if (ret == 0 && speed != EC_FAN_SPEED_NOT_PRESENT) + priv->usable_fans |= BIT(i); + } +} + +static int cros_ec_hwmon_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct cros_ec_dev *ec_dev = dev_get_drvdata(dev->parent); + struct cros_ec_device *cros_ec = ec_dev->ec_dev; + struct cros_ec_hwmon_priv *priv; + struct device *hwmon_dev; + u8 thermal_version; + int ret; + + ret = cros_ec_cmd_readmem(cros_ec, EC_MEMMAP_THERMAL_VERSION, 1, &thermal_version); + if (ret < 0) + return ret; + + /* Covers both fan and temp sensors */ + if (thermal_version == 0) + return -ENODEV; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->cros_ec = cros_ec; + + cros_ec_hwmon_probe_temp_sensors(dev, priv, thermal_version); + cros_ec_hwmon_probe_fans(priv); + + hwmon_dev = devm_hwmon_device_register_with_info(dev, "cros_ec", priv, + &cros_ec_hwmon_chip_info, NULL); + + return PTR_ERR_OR_ZERO(hwmon_dev); +} + +static const struct platform_device_id cros_ec_hwmon_id[] = { + { DRV_NAME, 0 }, + {} +}; + +static struct platform_driver cros_ec_hwmon_driver = { + .driver.name = DRV_NAME, + .probe = cros_ec_hwmon_probe, + .id_table = cros_ec_hwmon_id, +}; +module_platform_driver(cros_ec_hwmon_driver); + +MODULE_DEVICE_TABLE(platform, cros_ec_hwmon_id); +MODULE_DESCRIPTION("ChromeOS EC Hardware Monitoring Driver"); +MODULE_AUTHOR("Thomas Weißschuh Date: Tue, 4 Jun 2024 10:01:48 -0700 Subject: [PATCH 07/28] platform/chrome: Add struct ec_response_get_next_event_v3 Add struct ec_response_get_next_event_v3 to upgrade EC_CMD_GET_NEXT_EVENT to version 3. Signed-off-by: Daisuke Nojiri Link: https://lore.kernel.org/r/20240604170552.2517189-1-dnojiri@chromium.org Signed-off-by: Tzung-Bi Shih --- .../linux/platform_data/cros_ec_commands.h | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/include/linux/platform_data/cros_ec_commands.h b/include/linux/platform_data/cros_ec_commands.h index ecc47d5fe23906..ec598057d1dab5 100644 --- a/include/linux/platform_data/cros_ec_commands.h +++ b/include/linux/platform_data/cros_ec_commands.h @@ -3463,6 +3463,34 @@ union __ec_align_offset1 ec_response_get_next_data_v1 { }; BUILD_ASSERT(sizeof(union ec_response_get_next_data_v1) == 16); +union __ec_align_offset1 ec_response_get_next_data_v3 { + uint8_t key_matrix[18]; + + /* Unaligned */ + uint32_t host_event; + uint64_t host_event64; + + struct __ec_todo_unpacked { + /* For aligning the fifo_info */ + uint8_t reserved[3]; + struct ec_response_motion_sense_fifo_info info; + } sensor_fifo; + + uint32_t buttons; + + uint32_t switches; + + uint32_t fp_events; + + uint32_t sysrq; + + /* CEC events from enum mkbp_cec_event */ + uint32_t cec_events; + + uint8_t cec_message[16]; +}; +BUILD_ASSERT(sizeof(union ec_response_get_next_data_v3) == 18); + struct ec_response_get_next_event { uint8_t event_type; /* Followed by event data if any */ @@ -3475,6 +3503,12 @@ struct ec_response_get_next_event_v1 { union ec_response_get_next_data_v1 data; } __ec_align1; +struct ec_response_get_next_event_v3 { + uint8_t event_type; + /* Followed by event data if any */ + union ec_response_get_next_data_v3 data; +} __ec_align1; + /* Bit indices for buttons and switches.*/ /* Buttons */ #define EC_MKBP_POWER_BUTTON 0 From 106d6739823369c734a8fc3b13634274eee4f60e Mon Sep 17 00:00:00 2001 From: Daisuke Nojiri Date: Tue, 4 Jun 2024 16:08:25 -0700 Subject: [PATCH 08/28] platform/chrome: cros_ec_proto: Upgrade get_next_event to v3 Upgrade EC_CMD_GET_NEXT_EVENT to version 3. The max supported version will be v3. So, we speak v3 even if the EC says it supports v4+. Signed-off-by: Daisuke Nojiri Link: https://lore.kernel.org/r/20240604230837.2878737-1-dnojiri@chromium.org [tzungbi: uint32_t -> u32 per suggested by checkpatch.pl] Signed-off-by: Tzung-Bi Shih --- drivers/platform/chrome/cros_ec_proto.c | 27 ++++++++++++++------- include/linux/platform_data/cros_ec_proto.h | 2 +- 2 files changed, 19 insertions(+), 10 deletions(-) diff --git a/drivers/platform/chrome/cros_ec_proto.c b/drivers/platform/chrome/cros_ec_proto.c index 2ad1b8221ec0dc..fe68be66ee988d 100644 --- a/drivers/platform/chrome/cros_ec_proto.c +++ b/drivers/platform/chrome/cros_ec_proto.c @@ -684,7 +684,7 @@ EXPORT_SYMBOL(cros_ec_cmd_xfer_status); static int get_next_event_xfer(struct cros_ec_device *ec_dev, struct cros_ec_command *msg, - struct ec_response_get_next_event_v1 *event, + struct ec_response_get_next_event_v3 *event, int version, uint32_t size) { int ret; @@ -707,11 +707,12 @@ static int get_next_event(struct cros_ec_device *ec_dev) { struct { struct cros_ec_command msg; - struct ec_response_get_next_event_v1 event; + struct ec_response_get_next_event_v3 event; } __packed buf; struct cros_ec_command *msg = &buf.msg; - struct ec_response_get_next_event_v1 *event = &buf.event; - const int cmd_version = ec_dev->mkbp_event_supported - 1; + struct ec_response_get_next_event_v3 *event = &buf.event; + int cmd_version = ec_dev->mkbp_event_supported - 1; + u32 size; memset(msg, 0, sizeof(*msg)); if (ec_dev->suspended) { @@ -719,12 +720,20 @@ static int get_next_event(struct cros_ec_device *ec_dev) return -EHOSTDOWN; } - if (cmd_version == 0) - return get_next_event_xfer(ec_dev, msg, event, 0, - sizeof(struct ec_response_get_next_event)); + if (cmd_version == 0) { + size = sizeof(struct ec_response_get_next_event); + } else if (cmd_version < 3) { + size = sizeof(struct ec_response_get_next_event_v1); + } else { + /* + * The max version we support is v3. So, we speak v3 even if the + * EC says it supports v4+. + */ + cmd_version = 3; + size = sizeof(struct ec_response_get_next_event_v3); + } - return get_next_event_xfer(ec_dev, msg, event, cmd_version, - sizeof(struct ec_response_get_next_event_v1)); + return get_next_event_xfer(ec_dev, msg, event, cmd_version, size); } static int get_keyboard_state_event(struct cros_ec_device *ec_dev) diff --git a/include/linux/platform_data/cros_ec_proto.h b/include/linux/platform_data/cros_ec_proto.h index 1ddc52603f9ae2..6e9225bdf903d1 100644 --- a/include/linux/platform_data/cros_ec_proto.h +++ b/include/linux/platform_data/cros_ec_proto.h @@ -185,7 +185,7 @@ struct cros_ec_device { bool host_sleep_v1; struct blocking_notifier_head event_notifier; - struct ec_response_get_next_event_v1 event_data; + struct ec_response_get_next_event_v3 event_data; int event_size; u32 host_event_wake_mask; u32 last_resume_result; From 68dbac0a58ef7d82bc78dcb7e5ab5db2c6dfb489 Mon Sep 17 00:00:00 2001 From: Ben Walsh Date: Wed, 5 Jun 2024 07:33:47 +0100 Subject: [PATCH 09/28] platform/chrome: cros_ec_lpc: MEC access can return error code cros_ec_lpc_io_bytes_mec was returning a u8 checksum of all bytes read/written, which didn't leave room to indicate errors. Change this u8 to an int where negative values indicate an error, and non-negative values are the checksum as before. Tested-by: Dustin L. Howett Signed-off-by: Ben Walsh Link: https://lore.kernel.org/r/20240605063351.14836-2-ben@jubnut.com Signed-off-by: Tzung-Bi Shih --- drivers/platform/chrome/cros_ec_lpc.c | 130 ++++++++++++++------- drivers/platform/chrome/cros_ec_lpc_mec.c | 9 +- drivers/platform/chrome/cros_ec_lpc_mec.h | 7 +- drivers/platform/chrome/wilco_ec/mailbox.c | 22 ++-- 4 files changed, 112 insertions(+), 56 deletions(-) diff --git a/drivers/platform/chrome/cros_ec_lpc.c b/drivers/platform/chrome/cros_ec_lpc.c index ddfbfec44f4ccf..7bf13c1d2c670e 100644 --- a/drivers/platform/chrome/cros_ec_lpc.c +++ b/drivers/platform/chrome/cros_ec_lpc.c @@ -62,14 +62,16 @@ struct cros_ec_lpc { /** * struct lpc_driver_ops - LPC driver operations - * @read: Copy length bytes from EC address offset into buffer dest. Returns - * the 8-bit checksum of all bytes read. - * @write: Copy length bytes from buffer msg into EC address offset. Returns - * the 8-bit checksum of all bytes written. + * @read: Copy length bytes from EC address offset into buffer dest. + * Returns a negative error code on error, or the 8-bit checksum + * of all bytes read. + * @write: Copy length bytes from buffer msg into EC address offset. + * Returns a negative error code on error, or the 8-bit checksum + * of all bytes written. */ struct lpc_driver_ops { - u8 (*read)(unsigned int offset, unsigned int length, u8 *dest); - u8 (*write)(unsigned int offset, unsigned int length, const u8 *msg); + int (*read)(unsigned int offset, unsigned int length, u8 *dest); + int (*write)(unsigned int offset, unsigned int length, const u8 *msg); }; static struct lpc_driver_ops cros_ec_lpc_ops = { }; @@ -78,10 +80,10 @@ static struct lpc_driver_ops cros_ec_lpc_ops = { }; * A generic instance of the read function of struct lpc_driver_ops, used for * the LPC EC. */ -static u8 cros_ec_lpc_read_bytes(unsigned int offset, unsigned int length, - u8 *dest) +static int cros_ec_lpc_read_bytes(unsigned int offset, unsigned int length, + u8 *dest) { - int sum = 0; + u8 sum = 0; int i; for (i = 0; i < length; ++i) { @@ -97,10 +99,10 @@ static u8 cros_ec_lpc_read_bytes(unsigned int offset, unsigned int length, * A generic instance of the write function of struct lpc_driver_ops, used for * the LPC EC. */ -static u8 cros_ec_lpc_write_bytes(unsigned int offset, unsigned int length, - const u8 *msg) +static int cros_ec_lpc_write_bytes(unsigned int offset, unsigned int length, + const u8 *msg) { - int sum = 0; + u8 sum = 0; int i; for (i = 0; i < length; ++i) { @@ -116,8 +118,8 @@ static u8 cros_ec_lpc_write_bytes(unsigned int offset, unsigned int length, * An instance of the read function of struct lpc_driver_ops, used for the * MEC variant of LPC EC. */ -static u8 cros_ec_lpc_mec_read_bytes(unsigned int offset, unsigned int length, - u8 *dest) +static int cros_ec_lpc_mec_read_bytes(unsigned int offset, unsigned int length, + u8 *dest) { int in_range = cros_ec_lpc_mec_in_range(offset, length); @@ -135,8 +137,8 @@ static u8 cros_ec_lpc_mec_read_bytes(unsigned int offset, unsigned int length, * An instance of the write function of struct lpc_driver_ops, used for the * MEC variant of LPC EC. */ -static u8 cros_ec_lpc_mec_write_bytes(unsigned int offset, unsigned int length, - const u8 *msg) +static int cros_ec_lpc_mec_write_bytes(unsigned int offset, unsigned int length, + const u8 *msg) { int in_range = cros_ec_lpc_mec_in_range(offset, length); @@ -154,11 +156,14 @@ static int ec_response_timed_out(void) { unsigned long one_second = jiffies + HZ; u8 data; + int ret; usleep_range(200, 300); do { - if (!(cros_ec_lpc_ops.read(EC_LPC_ADDR_HOST_CMD, 1, &data) & - EC_LPC_STATUS_BUSY_MASK)) + ret = cros_ec_lpc_ops.read(EC_LPC_ADDR_HOST_CMD, 1, &data); + if (ret < 0) + return ret; + if (!(data & EC_LPC_STATUS_BUSY_MASK)) return 0; usleep_range(100, 200); } while (time_before(jiffies, one_second)); @@ -179,28 +184,41 @@ static int cros_ec_pkt_xfer_lpc(struct cros_ec_device *ec, goto done; /* Write buffer */ - cros_ec_lpc_ops.write(EC_LPC_ADDR_HOST_PACKET, ret, ec->dout); + ret = cros_ec_lpc_ops.write(EC_LPC_ADDR_HOST_PACKET, ret, ec->dout); + if (ret < 0) + goto done; /* Here we go */ sum = EC_COMMAND_PROTOCOL_3; - cros_ec_lpc_ops.write(EC_LPC_ADDR_HOST_CMD, 1, &sum); + ret = cros_ec_lpc_ops.write(EC_LPC_ADDR_HOST_CMD, 1, &sum); + if (ret < 0) + goto done; - if (ec_response_timed_out()) { + ret = ec_response_timed_out(); + if (ret < 0) + goto done; + if (ret) { dev_warn(ec->dev, "EC response timed out\n"); ret = -EIO; goto done; } /* Check result */ - msg->result = cros_ec_lpc_ops.read(EC_LPC_ADDR_HOST_DATA, 1, &sum); + ret = cros_ec_lpc_ops.read(EC_LPC_ADDR_HOST_DATA, 1, &sum); + if (ret < 0) + goto done; + msg->result = ret; ret = cros_ec_check_result(ec, msg); if (ret) goto done; /* Read back response */ dout = (u8 *)&response; - sum = cros_ec_lpc_ops.read(EC_LPC_ADDR_HOST_PACKET, sizeof(response), + ret = cros_ec_lpc_ops.read(EC_LPC_ADDR_HOST_PACKET, sizeof(response), dout); + if (ret < 0) + goto done; + sum = ret; msg->result = response.result; @@ -213,9 +231,12 @@ static int cros_ec_pkt_xfer_lpc(struct cros_ec_device *ec, } /* Read response and process checksum */ - sum += cros_ec_lpc_ops.read(EC_LPC_ADDR_HOST_PACKET + - sizeof(response), response.data_len, - msg->data); + ret = cros_ec_lpc_ops.read(EC_LPC_ADDR_HOST_PACKET + + sizeof(response), response.data_len, + msg->data); + if (ret < 0) + goto done; + sum += ret; if (sum) { dev_err(ec->dev, @@ -255,32 +276,47 @@ static int cros_ec_cmd_xfer_lpc(struct cros_ec_device *ec, sum = msg->command + args.flags + args.command_version + args.data_size; /* Copy data and update checksum */ - sum += cros_ec_lpc_ops.write(EC_LPC_ADDR_HOST_PARAM, msg->outsize, - msg->data); + ret = cros_ec_lpc_ops.write(EC_LPC_ADDR_HOST_PARAM, msg->outsize, + msg->data); + if (ret < 0) + goto done; + sum += ret; /* Finalize checksum and write args */ args.checksum = sum; - cros_ec_lpc_ops.write(EC_LPC_ADDR_HOST_ARGS, sizeof(args), - (u8 *)&args); + ret = cros_ec_lpc_ops.write(EC_LPC_ADDR_HOST_ARGS, sizeof(args), + (u8 *)&args); + if (ret < 0) + goto done; /* Here we go */ sum = msg->command; - cros_ec_lpc_ops.write(EC_LPC_ADDR_HOST_CMD, 1, &sum); + ret = cros_ec_lpc_ops.write(EC_LPC_ADDR_HOST_CMD, 1, &sum); + if (ret < 0) + goto done; - if (ec_response_timed_out()) { + ret = ec_response_timed_out(); + if (ret < 0) + goto done; + if (ret) { dev_warn(ec->dev, "EC response timed out\n"); ret = -EIO; goto done; } /* Check result */ - msg->result = cros_ec_lpc_ops.read(EC_LPC_ADDR_HOST_DATA, 1, &sum); + ret = cros_ec_lpc_ops.read(EC_LPC_ADDR_HOST_DATA, 1, &sum); + if (ret < 0) + goto done; + msg->result = ret; ret = cros_ec_check_result(ec, msg); if (ret) goto done; /* Read back args */ - cros_ec_lpc_ops.read(EC_LPC_ADDR_HOST_ARGS, sizeof(args), (u8 *)&args); + ret = cros_ec_lpc_ops.read(EC_LPC_ADDR_HOST_ARGS, sizeof(args), (u8 *)&args); + if (ret < 0) + goto done; if (args.data_size > msg->insize) { dev_err(ec->dev, @@ -294,8 +330,11 @@ static int cros_ec_cmd_xfer_lpc(struct cros_ec_device *ec, sum = msg->command + args.flags + args.command_version + args.data_size; /* Read response and update checksum */ - sum += cros_ec_lpc_ops.read(EC_LPC_ADDR_HOST_PARAM, args.data_size, - msg->data); + ret = cros_ec_lpc_ops.read(EC_LPC_ADDR_HOST_PARAM, args.data_size, + msg->data); + if (ret < 0) + goto done; + sum += ret; /* Verify checksum */ if (args.checksum != sum) { @@ -320,19 +359,24 @@ static int cros_ec_lpc_readmem(struct cros_ec_device *ec, unsigned int offset, int i = offset; char *s = dest; int cnt = 0; + int ret; if (offset >= EC_MEMMAP_SIZE - bytes) return -EINVAL; /* fixed length */ if (bytes) { - cros_ec_lpc_ops.read(ec_lpc->mmio_memory_base + offset, bytes, s); + ret = cros_ec_lpc_ops.read(ec_lpc->mmio_memory_base + offset, bytes, s); + if (ret < 0) + return ret; return bytes; } /* string */ for (; i < EC_MEMMAP_SIZE; i++, s++) { - cros_ec_lpc_ops.read(ec_lpc->mmio_memory_base + i, 1, s); + ret = cros_ec_lpc_ops.read(ec_lpc->mmio_memory_base + i, 1, s); + if (ret < 0) + return ret; cnt++; if (!*s) break; @@ -425,7 +469,9 @@ static int cros_ec_lpc_probe(struct platform_device *pdev) */ cros_ec_lpc_ops.read = cros_ec_lpc_mec_read_bytes; cros_ec_lpc_ops.write = cros_ec_lpc_mec_write_bytes; - cros_ec_lpc_ops.read(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_ID, 2, buf); + ret = cros_ec_lpc_ops.read(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_ID, 2, buf); + if (ret < 0) + return ret; if (buf[0] != 'E' || buf[1] != 'C') { if (!devm_request_region(dev, ec_lpc->mmio_memory_base, EC_MEMMAP_SIZE, dev_name(dev))) { @@ -436,8 +482,10 @@ static int cros_ec_lpc_probe(struct platform_device *pdev) /* Re-assign read/write operations for the non MEC variant */ cros_ec_lpc_ops.read = cros_ec_lpc_read_bytes; cros_ec_lpc_ops.write = cros_ec_lpc_write_bytes; - cros_ec_lpc_ops.read(ec_lpc->mmio_memory_base + EC_MEMMAP_ID, 2, - buf); + ret = cros_ec_lpc_ops.read(ec_lpc->mmio_memory_base + EC_MEMMAP_ID, 2, + buf); + if (ret < 0) + return ret; if (buf[0] != 'E' || buf[1] != 'C') { dev_err(dev, "EC ID not detected\n"); return -ENODEV; diff --git a/drivers/platform/chrome/cros_ec_lpc_mec.c b/drivers/platform/chrome/cros_ec_lpc_mec.c index 0d9c79b270ce20..395dc3a6fb5efc 100644 --- a/drivers/platform/chrome/cros_ec_lpc_mec.c +++ b/drivers/platform/chrome/cros_ec_lpc_mec.c @@ -67,11 +67,12 @@ int cros_ec_lpc_mec_in_range(unsigned int offset, unsigned int length) * @length: Number of bytes to read / write * @buf: Destination / source buffer * - * Return: 8-bit checksum of all bytes read / written + * @return: A negative error code on error, or 8-bit checksum of all + * bytes read / written */ -u8 cros_ec_lpc_io_bytes_mec(enum cros_ec_lpc_mec_io_type io_type, - unsigned int offset, unsigned int length, - u8 *buf) +int cros_ec_lpc_io_bytes_mec(enum cros_ec_lpc_mec_io_type io_type, + unsigned int offset, unsigned int length, + u8 *buf) { int i = 0; int io_addr; diff --git a/drivers/platform/chrome/cros_ec_lpc_mec.h b/drivers/platform/chrome/cros_ec_lpc_mec.h index 9d0521b23e8aed..69670832f187b1 100644 --- a/drivers/platform/chrome/cros_ec_lpc_mec.h +++ b/drivers/platform/chrome/cros_ec_lpc_mec.h @@ -64,9 +64,10 @@ int cros_ec_lpc_mec_in_range(unsigned int offset, unsigned int length); * @length: Number of bytes to read / write * @buf: Destination / source buffer * - * @return 8-bit checksum of all bytes read / written + * @return: A negative error code on error, or 8-bit checksum of all + * bytes read / written */ -u8 cros_ec_lpc_io_bytes_mec(enum cros_ec_lpc_mec_io_type io_type, - unsigned int offset, unsigned int length, u8 *buf); +int cros_ec_lpc_io_bytes_mec(enum cros_ec_lpc_mec_io_type io_type, + unsigned int offset, unsigned int length, u8 *buf); #endif /* __CROS_EC_LPC_MEC_H */ diff --git a/drivers/platform/chrome/wilco_ec/mailbox.c b/drivers/platform/chrome/wilco_ec/mailbox.c index 0f98358ea824c6..4d8273b47cdeea 100644 --- a/drivers/platform/chrome/wilco_ec/mailbox.c +++ b/drivers/platform/chrome/wilco_ec/mailbox.c @@ -117,13 +117,17 @@ static int wilco_ec_transfer(struct wilco_ec_device *ec, struct wilco_ec_request *rq) { struct wilco_ec_response *rs; - u8 checksum; + int ret; u8 flag; /* Write request header, then data */ - cros_ec_lpc_io_bytes_mec(MEC_IO_WRITE, 0, sizeof(*rq), (u8 *)rq); - cros_ec_lpc_io_bytes_mec(MEC_IO_WRITE, sizeof(*rq), msg->request_size, - msg->request_data); + ret = cros_ec_lpc_io_bytes_mec(MEC_IO_WRITE, 0, sizeof(*rq), (u8 *)rq); + if (ret < 0) + return ret; + ret = cros_ec_lpc_io_bytes_mec(MEC_IO_WRITE, sizeof(*rq), msg->request_size, + msg->request_data); + if (ret < 0) + return ret; /* Start the command */ outb(EC_MAILBOX_START_COMMAND, ec->io_command->start); @@ -149,10 +153,12 @@ static int wilco_ec_transfer(struct wilco_ec_device *ec, /* Read back response */ rs = ec->data_buffer; - checksum = cros_ec_lpc_io_bytes_mec(MEC_IO_READ, 0, - sizeof(*rs) + EC_MAILBOX_DATA_SIZE, - (u8 *)rs); - if (checksum) { + ret = cros_ec_lpc_io_bytes_mec(MEC_IO_READ, 0, + sizeof(*rs) + EC_MAILBOX_DATA_SIZE, + (u8 *)rs); + if (ret < 0) + return ret; + if (ret) { dev_dbg(ec->dev, "bad packet checksum 0x%02x\n", rs->checksum); return -EBADMSG; } From 60c7df66450e3a7821a8d68496c20c95de6a15c5 Mon Sep 17 00:00:00 2001 From: Ben Walsh Date: Wed, 5 Jun 2024 07:33:48 +0100 Subject: [PATCH 10/28] platform/chrome: cros_ec_lpc: MEC access can use an AML mutex Framework Laptops have ACPI code which accesses the MEC memory. It uses an AML mutex to prevent concurrent access. But the cros_ec_lpc driver was not aware of this mutex. The ACPI code and LPC driver both attempted to talk to the EC at the same time, messing up communication with the EC. Allow the LPC driver MEC code to find and use the AML mutex. Tested-by: Dustin L. Howett Signed-off-by: Ben Walsh Link: https://lore.kernel.org/r/20240605063351.14836-3-ben@jubnut.com Signed-off-by: Tzung-Bi Shih --- drivers/platform/chrome/cros_ec_lpc_mec.c | 76 ++++++++++++++++++++++- drivers/platform/chrome/cros_ec_lpc_mec.h | 11 ++++ 2 files changed, 85 insertions(+), 2 deletions(-) diff --git a/drivers/platform/chrome/cros_ec_lpc_mec.c b/drivers/platform/chrome/cros_ec_lpc_mec.c index 395dc3a6fb5efc..dfad934e65ca60 100644 --- a/drivers/platform/chrome/cros_ec_lpc_mec.c +++ b/drivers/platform/chrome/cros_ec_lpc_mec.c @@ -10,13 +10,65 @@ #include "cros_ec_lpc_mec.h" +#define ACPI_LOCK_DELAY_MS 500 + /* * This mutex must be held while accessing the EMI unit. We can't rely on the * EC mutex because memmap data may be accessed without it being held. */ static DEFINE_MUTEX(io_mutex); +/* + * An alternative mutex to be used when the ACPI AML code may also + * access memmap data. When set, this mutex is used in preference to + * io_mutex. + */ +static acpi_handle aml_mutex; + static u16 mec_emi_base, mec_emi_end; +/** + * cros_ec_lpc_mec_lock() - Acquire mutex for EMI + * + * @return: Negative error code, or zero for success + */ +static int cros_ec_lpc_mec_lock(void) +{ + bool success; + + if (!aml_mutex) { + mutex_lock(&io_mutex); + return 0; + } + + success = ACPI_SUCCESS(acpi_acquire_mutex(aml_mutex, + NULL, ACPI_LOCK_DELAY_MS)); + if (!success) + return -EBUSY; + + return 0; +} + +/** + * cros_ec_lpc_mec_unlock() - Release mutex for EMI + * + * @return: Negative error code, or zero for success + */ +static int cros_ec_lpc_mec_unlock(void) +{ + bool success; + + if (!aml_mutex) { + mutex_unlock(&io_mutex); + return 0; + } + + success = ACPI_SUCCESS(acpi_release_mutex(aml_mutex, NULL)); + if (!success) + return -EBUSY; + + return 0; +} + /** * cros_ec_lpc_mec_emi_write_address() - Initialize EMI at a given address. * @@ -78,6 +130,7 @@ int cros_ec_lpc_io_bytes_mec(enum cros_ec_lpc_mec_io_type io_type, int io_addr; u8 sum = 0; enum cros_ec_lpc_mec_emi_access_mode access, new_access; + int ret; /* Return checksum of 0 if window is not initialized */ WARN_ON(mec_emi_base == 0 || mec_emi_end == 0); @@ -93,7 +146,9 @@ int cros_ec_lpc_io_bytes_mec(enum cros_ec_lpc_mec_io_type io_type, else access = ACCESS_TYPE_LONG_AUTO_INCREMENT; - mutex_lock(&io_mutex); + ret = cros_ec_lpc_mec_lock(); + if (ret) + return ret; /* Initialize I/O at desired address */ cros_ec_lpc_mec_emi_write_address(offset, access); @@ -135,7 +190,9 @@ int cros_ec_lpc_io_bytes_mec(enum cros_ec_lpc_mec_io_type io_type, } done: - mutex_unlock(&io_mutex); + ret = cros_ec_lpc_mec_unlock(); + if (ret) + return ret; return sum; } @@ -147,3 +204,18 @@ void cros_ec_lpc_mec_init(unsigned int base, unsigned int end) mec_emi_end = end; } EXPORT_SYMBOL(cros_ec_lpc_mec_init); + +int cros_ec_lpc_mec_acpi_mutex(struct acpi_device *adev, const char *pathname) +{ + int status; + + if (!adev) + return -ENOENT; + + status = acpi_get_handle(adev->handle, pathname, &aml_mutex); + if (ACPI_FAILURE(status)) + return -ENOENT; + + return 0; +} +EXPORT_SYMBOL(cros_ec_lpc_mec_acpi_mutex); diff --git a/drivers/platform/chrome/cros_ec_lpc_mec.h b/drivers/platform/chrome/cros_ec_lpc_mec.h index 69670832f187b1..69f9d8786f61c0 100644 --- a/drivers/platform/chrome/cros_ec_lpc_mec.h +++ b/drivers/platform/chrome/cros_ec_lpc_mec.h @@ -8,6 +8,8 @@ #ifndef __CROS_EC_LPC_MEC_H #define __CROS_EC_LPC_MEC_H +#include + enum cros_ec_lpc_mec_emi_access_mode { /* 8-bit access */ ACCESS_TYPE_BYTE = 0x0, @@ -45,6 +47,15 @@ enum cros_ec_lpc_mec_io_type { */ void cros_ec_lpc_mec_init(unsigned int base, unsigned int end); +/** + * cros_ec_lpc_mec_acpi_mutex() - Find and set ACPI mutex for MEC + * + * @adev: Parent ACPI device + * @pathname: Name of AML mutex + * @return: Negative error code, or zero for success + */ +int cros_ec_lpc_mec_acpi_mutex(struct acpi_device *adev, const char *pathname); + /** * cros_ec_lpc_mec_in_range() - Determine if addresses are in MEC EMI range. * From 040159e0912c31fe959d8671f9700bda105ab63a Mon Sep 17 00:00:00 2001 From: Ben Walsh Date: Wed, 5 Jun 2024 07:33:49 +0100 Subject: [PATCH 11/28] platform/chrome: cros_ec_lpc: Add a new quirk for ACPI id Framework Laptops' ACPI exposes the EC with id "PNP0C09". But "PNP0C09" is part of the ACPI standard; there are lots of computers with EC chips with this id, and most of them don't support the cros_ec protocol. The driver could find the ACPI device by having "PNP0C09" in the acpi_match_table, but this would match devices which don't support the cros_ec protocol. Instead, add a new quirk "CROS_EC_LPC_QUIRK_ACPI_ID" which allows the id to be specified. This quirk is applied after the DMI check shows that the device is supported. Tested-by: Dustin L. Howett Signed-off-by: Ben Walsh Link: https://lore.kernel.org/r/20240605063351.14836-4-ben@jubnut.com Signed-off-by: Tzung-Bi Shih --- drivers/platform/chrome/cros_ec_lpc.c | 50 ++++++++++++++++++++------- 1 file changed, 38 insertions(+), 12 deletions(-) diff --git a/drivers/platform/chrome/cros_ec_lpc.c b/drivers/platform/chrome/cros_ec_lpc.c index 7bf13c1d2c670e..fa6606da802a05 100644 --- a/drivers/platform/chrome/cros_ec_lpc.c +++ b/drivers/platform/chrome/cros_ec_lpc.c @@ -39,6 +39,11 @@ static bool cros_ec_lpc_acpi_device_found; * be used as the base port for EC mapped memory. */ #define CROS_EC_LPC_QUIRK_REMAP_MEMORY BIT(0) +/* + * Indicates that lpc_driver_data.quirk_acpi_id should be used to find + * the ACPI device. + */ +#define CROS_EC_LPC_QUIRK_ACPI_ID BIT(1) /** * struct lpc_driver_data - driver data attached to a DMI device ID to indicate @@ -46,10 +51,12 @@ static bool cros_ec_lpc_acpi_device_found; * @quirks: a bitfield composed of quirks from CROS_EC_LPC_QUIRK_* * @quirk_mmio_memory_base: The first I/O port addressing EC mapped memory (used * when quirk ...REMAP_MEMORY is set.) + * @quirk_acpi_id: An ACPI HID to be used to find the ACPI device. */ struct lpc_driver_data { u32 quirks; u16 quirk_mmio_memory_base; + const char *quirk_acpi_id; }; /** @@ -418,6 +425,26 @@ static void cros_ec_lpc_acpi_notify(acpi_handle device, u32 value, void *data) pm_system_wakeup(); } +static acpi_status cros_ec_lpc_parse_device(acpi_handle handle, u32 level, + void *context, void **retval) +{ + *(struct acpi_device **)context = acpi_fetch_acpi_dev(handle); + return AE_CTRL_TERMINATE; +} + +static struct acpi_device *cros_ec_lpc_get_device(const char *id) +{ + struct acpi_device *adev = NULL; + acpi_status status = acpi_get_devices(id, cros_ec_lpc_parse_device, + &adev, NULL); + if (ACPI_FAILURE(status)) { + pr_warn(DRV_NAME ": Looking for %s failed\n", id); + return NULL; + } + + return adev; +} + static int cros_ec_lpc_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -445,6 +472,16 @@ static int cros_ec_lpc_probe(struct platform_device *pdev) if (quirks & CROS_EC_LPC_QUIRK_REMAP_MEMORY) ec_lpc->mmio_memory_base = driver_data->quirk_mmio_memory_base; + + if (quirks & CROS_EC_LPC_QUIRK_ACPI_ID) { + adev = cros_ec_lpc_get_device(driver_data->quirk_acpi_id); + if (!adev) { + dev_err(dev, "failed to get ACPI device '%s'", + driver_data->quirk_acpi_id); + return -ENODEV; + } + ACPI_COMPANION_SET(dev, adev); + } } /* @@ -709,23 +746,12 @@ static struct platform_device cros_ec_lpc_device = { .name = DRV_NAME }; -static acpi_status cros_ec_lpc_parse_device(acpi_handle handle, u32 level, - void *context, void **retval) -{ - *(bool *)context = true; - return AE_CTRL_TERMINATE; -} - static int __init cros_ec_lpc_init(void) { int ret; - acpi_status status; const struct dmi_system_id *dmi_match; - status = acpi_get_devices(ACPI_DRV_NAME, cros_ec_lpc_parse_device, - &cros_ec_lpc_acpi_device_found, NULL); - if (ACPI_FAILURE(status)) - pr_warn(DRV_NAME ": Looking for %s failed\n", ACPI_DRV_NAME); + cros_ec_lpc_acpi_device_found = !!cros_ec_lpc_get_device(ACPI_DRV_NAME); dmi_match = dmi_first_match(cros_ec_lpc_dmi_table); From 38c31b1d737ba4cab571dbf9090a1cabf164bea2 Mon Sep 17 00:00:00 2001 From: Ben Walsh Date: Wed, 5 Jun 2024 07:33:50 +0100 Subject: [PATCH 12/28] platform/chrome: cros_ec_lpc: Add a new quirk for AML mutex Add a new quirk "CROS_EC_LPC_QUIRK_AML_MUTEX" which provides the name of an AML mutex to protect MEC memory access. Tested-by: Dustin L. Howett Signed-off-by: Ben Walsh Link: https://lore.kernel.org/r/20240605063351.14836-5-ben@jubnut.com Signed-off-by: Tzung-Bi Shih --- drivers/platform/chrome/cros_ec_lpc.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/platform/chrome/cros_ec_lpc.c b/drivers/platform/chrome/cros_ec_lpc.c index fa6606da802a05..5d9cc8df208bfc 100644 --- a/drivers/platform/chrome/cros_ec_lpc.c +++ b/drivers/platform/chrome/cros_ec_lpc.c @@ -44,6 +44,11 @@ static bool cros_ec_lpc_acpi_device_found; * the ACPI device. */ #define CROS_EC_LPC_QUIRK_ACPI_ID BIT(1) +/* + * Indicates that lpc_driver_data.quirk_aml_mutex_name should be used + * to find an AML mutex to protect access to Microchip EC. + */ +#define CROS_EC_LPC_QUIRK_AML_MUTEX BIT(2) /** * struct lpc_driver_data - driver data attached to a DMI device ID to indicate @@ -52,11 +57,14 @@ static bool cros_ec_lpc_acpi_device_found; * @quirk_mmio_memory_base: The first I/O port addressing EC mapped memory (used * when quirk ...REMAP_MEMORY is set.) * @quirk_acpi_id: An ACPI HID to be used to find the ACPI device. + * @quirk_aml_mutex_name: The name of an AML mutex to be used to protect access + * to Microchip EC. */ struct lpc_driver_data { u32 quirks; u16 quirk_mmio_memory_base; const char *quirk_acpi_id; + const char *quirk_aml_mutex_name; }; /** @@ -482,6 +490,17 @@ static int cros_ec_lpc_probe(struct platform_device *pdev) } ACPI_COMPANION_SET(dev, adev); } + + if (quirks & CROS_EC_LPC_QUIRK_AML_MUTEX) { + const char *name + = driver_data->quirk_aml_mutex_name; + ret = cros_ec_lpc_mec_acpi_mutex(ACPI_COMPANION(dev), name); + if (ret) { + dev_err(dev, "failed to get AML mutex '%s'", name); + return ret; + } + dev_info(dev, "got AML mutex '%s'", name); + } } /* From 04ca0a51f1e63bd553fd4af8e9af0fe094fa4f0a Mon Sep 17 00:00:00 2001 From: Ben Walsh Date: Wed, 5 Jun 2024 07:33:51 +0100 Subject: [PATCH 13/28] platform/chrome: cros_ec_lpc: Add quirks for Framework Laptop For Framework Laptops with Microchip EC (MEC), use the ACPI id "PNP0C09" to find the ACPI device, and AML mutex "ECMT" to protect EC memory access. Tested-by: Dustin L. Howett Signed-off-by: Ben Walsh Link: https://lore.kernel.org/r/20240605063351.14836-6-ben@jubnut.com Signed-off-by: Tzung-Bi Shih --- drivers/platform/chrome/cros_ec_lpc.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/platform/chrome/cros_ec_lpc.c b/drivers/platform/chrome/cros_ec_lpc.c index 5d9cc8df208bfc..ebe9fb143840d2 100644 --- a/drivers/platform/chrome/cros_ec_lpc.c +++ b/drivers/platform/chrome/cros_ec_lpc.c @@ -636,6 +636,12 @@ static const struct lpc_driver_data framework_laptop_amd_lpc_driver_data __initc .quirk_mmio_memory_base = 0xE00, }; +static const struct lpc_driver_data framework_laptop_11_lpc_driver_data __initconst = { + .quirks = CROS_EC_LPC_QUIRK_ACPI_ID|CROS_EC_LPC_QUIRK_AML_MUTEX, + .quirk_acpi_id = "PNP0C09", + .quirk_aml_mutex_name = "ECMT", +}; + static const struct dmi_system_id cros_ec_lpc_dmi_table[] __initconst = { { /* @@ -704,6 +710,7 @@ static const struct dmi_system_id cros_ec_lpc_dmi_table[] __initconst = { DMI_MATCH(DMI_SYS_VENDOR, "Framework"), DMI_MATCH(DMI_PRODUCT_NAME, "Laptop"), }, + .driver_data = (void *)&framework_laptop_11_lpc_driver_data, }, { /* sentinel */ } }; From 1f72dd046270ff44e5fd43045c4d0bb025f88607 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Thu, 6 Jun 2024 16:12:11 +0300 Subject: [PATCH 14/28] hwmon: (cros_ec) Prevent read overflow in probe() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The "resp.sensor_name" comes from cros_ec_cmd() and it hasn't necessarily been NUL terminated. We had not intended to read past "sensor_name_size" bytes, however, there is a width vs precision bug in the format string. The format needs to be precision '%.*s' instead of width '%*s'. Precision prevents an out of bounds read, but width is a no-op. Fixes: bc3e45258096 ("hwmon: add ChromeOS EC driver") Signed-off-by: Dan Carpenter Reviewed-by: Guenter Roeck Acked-by: Thomas Weißschuh Link: https://lore.kernel.org/r/42331b70-bd3c-496c-8c79-3ec4faad40b8@moroto.mountain Signed-off-by: Tzung-Bi Shih --- drivers/hwmon/cros_ec_hwmon.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/hwmon/cros_ec_hwmon.c b/drivers/hwmon/cros_ec_hwmon.c index 41f268fa826098..b3ba7247e06b2b 100644 --- a/drivers/hwmon/cros_ec_hwmon.c +++ b/drivers/hwmon/cros_ec_hwmon.c @@ -212,7 +212,7 @@ static void cros_ec_hwmon_probe_temp_sensors(struct device *dev, struct cros_ec_ continue; sensor_name_size = strnlen(resp.sensor_name, sizeof(resp.sensor_name)); - priv->temp_sensor_names[i] = devm_kasprintf(dev, GFP_KERNEL, "%*s", + priv->temp_sensor_names[i] = devm_kasprintf(dev, GFP_KERNEL, "%.*s", (int)sensor_name_size, resp.sensor_name); } From c8a4bdca928debacf49524d1b09dbf27e88e1f18 Mon Sep 17 00:00:00 2001 From: Guenter Roeck Date: Thu, 6 Jun 2024 11:05:07 -0700 Subject: [PATCH 15/28] hwmon: (cros_ec) Fix access to restricted __le16 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit 0-day complains: drivers-hwmon-cros_ec_hwmon.c:sparse:sparse:cast-to-restricted-__le16 Fix by using a __le16 typed variable as parameter to le16_to_cpu(). Fixes: bc3e45258096 ("hwmon: add ChromeOS EC driver") Cc: Thomas Weißschuh Cc: Tzung-Bi Shih Signed-off-by: Guenter Roeck Acked-by: Thomas Weißschuh Link: https://lore.kernel.org/r/20240606180507.3332237-1-linux@roeck-us.net Signed-off-by: Tzung-Bi Shih --- drivers/hwmon/cros_ec_hwmon.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/hwmon/cros_ec_hwmon.c b/drivers/hwmon/cros_ec_hwmon.c index b3ba7247e06b2b..5514cf780b8bea 100644 --- a/drivers/hwmon/cros_ec_hwmon.c +++ b/drivers/hwmon/cros_ec_hwmon.c @@ -26,12 +26,13 @@ struct cros_ec_hwmon_priv { static int cros_ec_hwmon_read_fan_speed(struct cros_ec_device *cros_ec, u8 index, u16 *speed) { int ret; + __le16 __speed; - ret = cros_ec_cmd_readmem(cros_ec, EC_MEMMAP_FAN + index * 2, 2, speed); + ret = cros_ec_cmd_readmem(cros_ec, EC_MEMMAP_FAN + index * 2, 2, &__speed); if (ret < 0) return ret; - *speed = le16_to_cpu(*speed); + *speed = le16_to_cpu(__speed); return 0; } From d11c00292a31537ae1e46ddea8f101f8822ede34 Mon Sep 17 00:00:00 2001 From: Jeff Johnson Date: Mon, 10 Jun 2024 14:50:37 -0700 Subject: [PATCH 16/28] platform/chrome: cros_ec_proto: add missing MODULE_DESCRIPTION() macro make allmodconfig && make W=1 C=1 reports: WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/platform/chrome/cros_kunit_proto_test.o Add the missing invocation of the MODULE_DESCRIPTION() macro. Signed-off-by: Jeff Johnson Link: https://lore.kernel.org/r/20240610-md-drivers-platform-chrome-v1-1-f9c75adcc1ca@quicinc.com Signed-off-by: Tzung-Bi Shih --- drivers/platform/chrome/cros_ec_proto_test.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/platform/chrome/cros_ec_proto_test.c b/drivers/platform/chrome/cros_ec_proto_test.c index 41378c2ee6a0dd..3960f7c16eb0c6 100644 --- a/drivers/platform/chrome/cros_ec_proto_test.c +++ b/drivers/platform/chrome/cros_ec_proto_test.c @@ -2740,4 +2740,5 @@ static struct kunit_suite cros_ec_proto_test_suite = { kunit_test_suite(cros_ec_proto_test_suite); +MODULE_DESCRIPTION("Kunit tests for ChromeOS Embedded Controller protocol"); MODULE_LICENSE("GPL"); From 41f1242f62490bc48520bf5d800d2c2c4e2258ec Mon Sep 17 00:00:00 2001 From: Tzung-Bi Shih Date: Tue, 11 Jun 2024 03:31:13 +0000 Subject: [PATCH 17/28] platform/chrome: cros_ec_proto: update Kunit test for get_next_data_v3 Since commit 106d67398233 ("platform/chrome: cros_ec_proto: Upgrade get_next_event to v3"), (struct cros_ec_device *)->event_data becomes struct ec_response_get_next_event_v3. Update the Kunit test for fixing the following error: > Expected mock->msg.insize == sizeof(union ec_response_get_next_data_v1), but > mock->msg.insize == 18 (0x12) > sizeof(union ec_response_get_next_data_v1) == 16 (0x10) Reviewed-by: Guenter Roeck Link: https://lore.kernel.org/r/20240611033113.4154548-1-tzungbi@kernel.org Signed-off-by: Tzung-Bi Shih --- drivers/platform/chrome/cros_ec_proto_test.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/platform/chrome/cros_ec_proto_test.c b/drivers/platform/chrome/cros_ec_proto_test.c index 3960f7c16eb0c6..7ca9895a0065ee 100644 --- a/drivers/platform/chrome/cros_ec_proto_test.c +++ b/drivers/platform/chrome/cros_ec_proto_test.c @@ -2060,17 +2060,17 @@ static void cros_ec_proto_test_get_next_event_no_mkbp_event(struct kunit *test) /* For get_keyboard_state_event(). */ { - union ec_response_get_next_data_v1 *data; + union ec_response_get_next_data_v3 *data; mock = cros_kunit_ec_xfer_mock_add(test, sizeof(*data)); KUNIT_ASSERT_PTR_NE(test, mock, NULL); - data = (union ec_response_get_next_data_v1 *)mock->o_data; + data = (union ec_response_get_next_data_v3 *)mock->o_data; data->host_event = 0xbeef; } ret = cros_ec_get_next_event(ec_dev, &wake_event, &more_events); - KUNIT_EXPECT_EQ(test, ret, sizeof(union ec_response_get_next_data_v1)); + KUNIT_EXPECT_EQ(test, ret, sizeof(union ec_response_get_next_data_v3)); KUNIT_EXPECT_EQ(test, ec_dev->event_data.event_type, EC_MKBP_EVENT_KEY_MATRIX); KUNIT_EXPECT_EQ(test, ec_dev->event_data.data.host_event, 0xbeef); @@ -2085,7 +2085,7 @@ static void cros_ec_proto_test_get_next_event_no_mkbp_event(struct kunit *test) KUNIT_EXPECT_EQ(test, mock->msg.version, 0); KUNIT_EXPECT_EQ(test, mock->msg.command, EC_CMD_MKBP_STATE); - KUNIT_EXPECT_EQ(test, mock->msg.insize, sizeof(union ec_response_get_next_data_v1)); + KUNIT_EXPECT_EQ(test, mock->msg.insize, sizeof(union ec_response_get_next_data_v3)); KUNIT_EXPECT_EQ(test, mock->msg.outsize, 0); } } From c2a28647bbb4e0894e8824362410f72b06ac57a4 Mon Sep 17 00:00:00 2001 From: Tzung-Bi Shih Date: Tue, 11 Jun 2024 11:31:10 +0000 Subject: [PATCH 18/28] platform/chrome: cros_ec_debugfs: fix wrong EC message version ec_read_version_supported() uses ec_params_get_cmd_versions_v1 but it wrongly uses message version 0. Fix it. Fixes: e86264595225 ("mfd: cros_ec: add debugfs, console log file") Reviewed-by: Guenter Roeck Link: https://lore.kernel.org/r/20240611113110.16955-1-tzungbi@kernel.org Signed-off-by: Tzung-Bi Shih --- drivers/platform/chrome/cros_ec_debugfs.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/platform/chrome/cros_ec_debugfs.c b/drivers/platform/chrome/cros_ec_debugfs.c index f0e9efb543df6c..4525ad1b59f448 100644 --- a/drivers/platform/chrome/cros_ec_debugfs.c +++ b/drivers/platform/chrome/cros_ec_debugfs.c @@ -334,6 +334,7 @@ static int ec_read_version_supported(struct cros_ec_dev *ec) if (!msg) return 0; + msg->version = 1; msg->command = EC_CMD_GET_CMD_VERSIONS + ec->cmd_offset; msg->outsize = sizeof(*params); msg->insize = sizeof(*response); From 77a714325d09e1527d865dc011ef91c4972ffedd Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Thu, 13 Jun 2024 16:55:14 +0300 Subject: [PATCH 19/28] platform/chrome: cros_ec_lpc: Fix error code in cros_ec_lpc_mec_read_bytes() We changed these functions to returning negative error codes, but this first error path was accidentally overlooked. It leads to a Smatch warning: drivers/platform/chrome/cros_ec_lpc.c:181 ec_response_timed_out() error: uninitialized symbol 'data'. Fix this by returning the error code instead of success. Fixes: 68dbac0a58ef ("platform/chrome: cros_ec_lpc: MEC access can return error code") Signed-off-by: Dan Carpenter Reviewed-by: Guenter Roeck Link: https://lore.kernel.org/r/e0b43fb5-ecc8-4fb4-9b76-c06dea8cc4c4@moroto.mountain Signed-off-by: Tzung-Bi Shih --- drivers/platform/chrome/cros_ec_lpc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/platform/chrome/cros_ec_lpc.c b/drivers/platform/chrome/cros_ec_lpc.c index ebe9fb143840d2..f0470248b10987 100644 --- a/drivers/platform/chrome/cros_ec_lpc.c +++ b/drivers/platform/chrome/cros_ec_lpc.c @@ -139,7 +139,7 @@ static int cros_ec_lpc_mec_read_bytes(unsigned int offset, unsigned int length, int in_range = cros_ec_lpc_mec_in_range(offset, length); if (in_range < 0) - return 0; + return in_range; return in_range ? cros_ec_lpc_io_bytes_mec(MEC_IO_READ, @@ -158,7 +158,7 @@ static int cros_ec_lpc_mec_write_bytes(unsigned int offset, unsigned int length, int in_range = cros_ec_lpc_mec_in_range(offset, length); if (in_range < 0) - return 0; + return in_range; return in_range ? cros_ec_lpc_io_bytes_mec(MEC_IO_WRITE, From b57cd5703a1618e87772094ac12c5ee7d6c35e2f Mon Sep 17 00:00:00 2001 From: Ben Walsh Date: Thu, 13 Jun 2024 22:25:42 +0100 Subject: [PATCH 20/28] platform/chrome: cros_ec_lpc: Handle zero length read/write cros_ec_lpc_mec_read_bytes and cros_ec_lpc_mec_write_bytes call cros_ec_lpc_mec_in_range, which checks if addresses are in the MEC address range, and returns -EINVAL if the range given is not sensible. However cros_ec_lpc_mec_in_range was also returning -EINVAL for a zero length range. A zero length range should not be an error condition. cros_ec_lpc_mec_in_range now returns 1 in this case. cros_ec_lpc_io_bytes_mec checks for zero length, and returns immediately without beginning a transfer. Fixes: 68dbac0a58ef ("platform/chrome: cros_ec_lpc: MEC access can return error code") Fixes: 77a714325d09 ("platform/chrome: cros_ec_lpc: Fix error code in cros_ec_lpc_mec_read_bytes()") Signed-off-by: Ben Walsh Link: https://lore.kernel.org/r/20240613212542.403-1-ben@jubnut.com Signed-off-by: Tzung-Bi Shih --- drivers/platform/chrome/cros_ec_lpc_mec.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/platform/chrome/cros_ec_lpc_mec.c b/drivers/platform/chrome/cros_ec_lpc_mec.c index dfad934e65ca60..a56584171168c3 100644 --- a/drivers/platform/chrome/cros_ec_lpc_mec.c +++ b/drivers/platform/chrome/cros_ec_lpc_mec.c @@ -93,9 +93,6 @@ static void cros_ec_lpc_mec_emi_write_address(u16 addr, */ int cros_ec_lpc_mec_in_range(unsigned int offset, unsigned int length) { - if (length == 0) - return -EINVAL; - if (WARN_ON(mec_emi_base == 0 || mec_emi_end == 0)) return -EINVAL; @@ -132,6 +129,9 @@ int cros_ec_lpc_io_bytes_mec(enum cros_ec_lpc_mec_io_type io_type, enum cros_ec_lpc_mec_emi_access_mode access, new_access; int ret; + if (length == 0) + return 0; + /* Return checksum of 0 if window is not initialized */ WARN_ON(mec_emi_base == 0 || mec_emi_end == 0); if (mec_emi_base == 0 || mec_emi_end == 0) From 5b8feca8dee443055049c8ccfdd97f64a0e1d2b4 Mon Sep 17 00:00:00 2001 From: Daisuke Nojiri Date: Thu, 27 Jun 2024 16:53:08 -0700 Subject: [PATCH 21/28] dt-bindings: input: cros-ec-keyboard: Add keyboard matrix v3.0 Add support for keyboard matrix version 3.0, which reduces keyboard ghosting. Signed-off-by: Daisuke Nojiri Acked-by: Krzysztof Kozlowski Reviewed-by: Dmitry Torokhov Link: https://lore.kernel.org/r/9ae4d96cc2ce8c9de8755b9beffb78c641100fe7.1719531519.git.dnojiri@chromium.org Signed-off-by: Tzung-Bi Shih --- include/dt-bindings/input/cros-ec-keyboard.h | 104 +++++++++++++++++++ 1 file changed, 104 insertions(+) diff --git a/include/dt-bindings/input/cros-ec-keyboard.h b/include/dt-bindings/input/cros-ec-keyboard.h index f0ae03634a9667..afc12f6aa642cb 100644 --- a/include/dt-bindings/input/cros-ec-keyboard.h +++ b/include/dt-bindings/input/cros-ec-keyboard.h @@ -100,4 +100,108 @@ MATRIX_KEY(0x07, 0x0b, KEY_UP) \ MATRIX_KEY(0x07, 0x0c, KEY_LEFT) +/* No numpad */ +#define CROS_TOP_ROW_KEYMAP_V30 \ + MATRIX_KEY(0x00, 0x01, KEY_F11) /* T11 */ \ + MATRIX_KEY(0x00, 0x02, KEY_F1) /* T1 */ \ + MATRIX_KEY(0x00, 0x04, KEY_F10) /* T10 */ \ + MATRIX_KEY(0x00, 0x0b, KEY_F14) /* T14 */ \ + MATRIX_KEY(0x00, 0x0c, KEY_F15) /* T15 */ \ + MATRIX_KEY(0x01, 0x02, KEY_F4) /* T4 */ \ + MATRIX_KEY(0x01, 0x04, KEY_F7) /* T7 */ \ + MATRIX_KEY(0x01, 0x05, KEY_F12) /* T12 */ \ + MATRIX_KEY(0x01, 0x09, KEY_F9) /* T9 */ \ + MATRIX_KEY(0x02, 0x02, KEY_F3) /* T3 */ \ + MATRIX_KEY(0x02, 0x04, KEY_F6) /* T6 */ \ + MATRIX_KEY(0x02, 0x0b, KEY_F8) /* T8 */ \ + MATRIX_KEY(0x03, 0x02, KEY_F2) /* T2 */ \ + MATRIX_KEY(0x03, 0x05, KEY_F13) /* T13 */ \ + MATRIX_KEY(0x04, 0x04, KEY_F5) /* T5 */ + +#define CROS_MAIN_KEYMAP_V30 /* Keycode */ \ + MATRIX_KEY(0x00, 0x03, KEY_B) /* 50 */ \ + MATRIX_KEY(0x00, 0x05, KEY_N) /* 51 */ \ + MATRIX_KEY(0x00, 0x06, KEY_RO) /* 56 (JIS) */ \ + MATRIX_KEY(0x00, 0x08, KEY_EQUAL) /* 13 */ \ + MATRIX_KEY(0x00, 0x09, KEY_HOME) /* 80 (Numpad) */ \ + MATRIX_KEY(0x00, 0x0a, KEY_RIGHTALT) /* 62 */ \ + MATRIX_KEY(0x00, 0x10, KEY_FN) /* 127 */ \ + \ + MATRIX_KEY(0x01, 0x01, KEY_ESC) /* 110 */ \ + MATRIX_KEY(0x01, 0x03, KEY_G) /* 35 */ \ + MATRIX_KEY(0x01, 0x06, KEY_H) /* 36 */ \ + MATRIX_KEY(0x01, 0x08, KEY_APOSTROPHE) /* 41 */ \ + MATRIX_KEY(0x01, 0x0b, KEY_BACKSPACE) /* 15 */ \ + MATRIX_KEY(0x01, 0x0c, KEY_HENKAN) /* 65 (JIS) */ \ + MATRIX_KEY(0x01, 0x0e, KEY_LEFTCTRL) /* 58 */ \ + \ + MATRIX_KEY(0x02, 0x01, KEY_TAB) /* 16 */ \ + MATRIX_KEY(0x02, 0x03, KEY_T) /* 21 */ \ + MATRIX_KEY(0x02, 0x05, KEY_RIGHTBRACE) /* 28 */ \ + MATRIX_KEY(0x02, 0x06, KEY_Y) /* 22 */ \ + MATRIX_KEY(0x02, 0x08, KEY_LEFTBRACE) /* 27 */ \ + MATRIX_KEY(0x02, 0x09, KEY_DELETE) /* 76 (Numpad) */ \ + MATRIX_KEY(0x02, 0x0c, KEY_PAGEUP) /* 85 (Numpad) */ \ + MATRIX_KEY(0x02, 0x011, KEY_YEN) /* 14 (JIS) */ \ + \ + MATRIX_KEY(0x03, 0x00, KEY_LEFTMETA) /* Launcher */ \ + MATRIX_KEY(0x03, 0x01, KEY_GRAVE) /* 1 */ \ + MATRIX_KEY(0x03, 0x03, KEY_5) /* 6 */ \ + MATRIX_KEY(0x03, 0x04, KEY_S) /* 32 */ \ + MATRIX_KEY(0x03, 0x06, KEY_MINUS) /* 12 */ \ + MATRIX_KEY(0x03, 0x08, KEY_6) /* 7 */ \ + MATRIX_KEY(0x03, 0x09, KEY_SLEEP) /* Lock */ \ + MATRIX_KEY(0x03, 0x0b, KEY_BACKSLASH) /* 29 */ \ + MATRIX_KEY(0x03, 0x0c, KEY_MUHENKAN) /* 63 (JIS) */ \ + MATRIX_KEY(0x03, 0x0e, KEY_RIGHTCTRL) /* 64 */ \ + \ + MATRIX_KEY(0x04, 0x01, KEY_A) /* 31 */ \ + MATRIX_KEY(0x04, 0x02, KEY_D) /* 33 */ \ + MATRIX_KEY(0x04, 0x03, KEY_F) /* 34 */ \ + MATRIX_KEY(0x04, 0x05, KEY_K) /* 38 */ \ + MATRIX_KEY(0x04, 0x06, KEY_J) /* 37 */ \ + MATRIX_KEY(0x04, 0x08, KEY_SEMICOLON) /* 40 */ \ + MATRIX_KEY(0x04, 0x09, KEY_L) /* 39 */ \ + MATRIX_KEY(0x04, 0x0b, KEY_ENTER) /* 43 */ \ + MATRIX_KEY(0x04, 0x0c, KEY_END) /* 81 (Numpad) */ \ + \ + MATRIX_KEY(0x05, 0x01, KEY_1) /* 2 */ \ + MATRIX_KEY(0x05, 0x02, KEY_COMMA) /* 53 */ \ + MATRIX_KEY(0x05, 0x03, KEY_DOT) /* 54 */ \ + MATRIX_KEY(0x05, 0x04, KEY_SLASH) /* 55 */ \ + MATRIX_KEY(0x05, 0x05, KEY_C) /* 48 */ \ + MATRIX_KEY(0x05, 0x06, KEY_SPACE) /* 61 */ \ + MATRIX_KEY(0x05, 0x07, KEY_LEFTSHIFT) /* 44 */ \ + MATRIX_KEY(0x05, 0x08, KEY_X) /* 47 */ \ + MATRIX_KEY(0x05, 0x09, KEY_V) /* 49 */ \ + MATRIX_KEY(0x05, 0x0b, KEY_M) /* 52 */ \ + MATRIX_KEY(0x05, 0x0c, KEY_PAGEDOWN) /* 86 (Numpad) */ \ + \ + MATRIX_KEY(0x06, 0x01, KEY_Z) /* 46 */ \ + MATRIX_KEY(0x06, 0x02, KEY_3) /* 4 */ \ + MATRIX_KEY(0x06, 0x03, KEY_4) /* 5 */ \ + MATRIX_KEY(0x06, 0x04, KEY_2) /* 3 */ \ + MATRIX_KEY(0x06, 0x05, KEY_8) /* 9 */ \ + MATRIX_KEY(0x06, 0x06, KEY_0) /* 11 */ \ + MATRIX_KEY(0x06, 0x08, KEY_7) /* 8 */ \ + MATRIX_KEY(0x06, 0x09, KEY_9) /* 10 */ \ + MATRIX_KEY(0x06, 0x0b, KEY_DOWN) /* 84 */ \ + MATRIX_KEY(0x06, 0x0c, KEY_RIGHT) /* 89 */ \ + MATRIX_KEY(0x06, 0x0d, KEY_LEFTALT) /* 60 */ \ + MATRIX_KEY(0x06, 0x0f, KEY_ASSISTANT) /* 128 */ \ + MATRIX_KEY(0x06, 0x11, KEY_BACKSLASH) /* 42 (JIS, ISO) */ \ + \ + MATRIX_KEY(0x07, 0x01, KEY_U) /* 23 */ \ + MATRIX_KEY(0x07, 0x02, KEY_I) /* 24 */ \ + MATRIX_KEY(0x07, 0x03, KEY_O) /* 25 */ \ + MATRIX_KEY(0x07, 0x04, KEY_P) /* 26 */ \ + MATRIX_KEY(0x07, 0x05, KEY_Q) /* 17 */ \ + MATRIX_KEY(0x07, 0x06, KEY_W) /* 18 */ \ + MATRIX_KEY(0x07, 0x07, KEY_RIGHTSHIFT) /* 57 */ \ + MATRIX_KEY(0x07, 0x08, KEY_E) /* 19 */ \ + MATRIX_KEY(0x07, 0x09, KEY_R) /* 20 */ \ + MATRIX_KEY(0x07, 0x0b, KEY_UP) /* 83 */ \ + MATRIX_KEY(0x07, 0x0c, KEY_LEFT) /* 79 */ \ + MATRIX_KEY(0x07, 0x11, KEY_102ND) /* 45 (ISO) */ + #endif /* _CROS_EC_KEYBOARD_H */ From 2681bbaa39cc2b5711494cc7e0166538f24e9c16 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Thomas=20Wei=C3=9Fschuh?= Date: Sun, 30 Jun 2024 22:54:08 +0200 Subject: [PATCH 22/28] ACPI: battery: add devm_battery_hook_register() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a utility function for device-managed registration of battery hooks. The function makes it easier to manage the lifecycle of a hook. Acked-by: Rafael J. Wysocki Signed-off-by: Thomas Weißschuh Link: https://lore.kernel.org/r/20240630-cros_ec-charge-control-v5-1-8f649d018c52@weissschuh.net Signed-off-by: Tzung-Bi Shih --- drivers/acpi/battery.c | 15 +++++++++++++++ include/acpi/battery.h | 2 ++ 2 files changed, 17 insertions(+) diff --git a/drivers/acpi/battery.c b/drivers/acpi/battery.c index b379401ff1c203..6ea979f76f847a 100644 --- a/drivers/acpi/battery.c +++ b/drivers/acpi/battery.c @@ -756,6 +756,21 @@ void battery_hook_register(struct acpi_battery_hook *hook) } EXPORT_SYMBOL_GPL(battery_hook_register); +static void devm_battery_hook_unregister(void *data) +{ + struct acpi_battery_hook *hook = data; + + battery_hook_unregister(hook); +} + +int devm_battery_hook_register(struct device *dev, struct acpi_battery_hook *hook) +{ + battery_hook_register(hook); + + return devm_add_action_or_reset(dev, devm_battery_hook_unregister, hook); +} +EXPORT_SYMBOL_GPL(devm_battery_hook_register); + /* * This function gets called right after the battery sysfs * attributes have been added, so that the drivers that diff --git a/include/acpi/battery.h b/include/acpi/battery.h index 611a2561a014f6..c93f16dfb944a0 100644 --- a/include/acpi/battery.h +++ b/include/acpi/battery.h @@ -2,6 +2,7 @@ #ifndef __ACPI_BATTERY_H #define __ACPI_BATTERY_H +#include #include #define ACPI_BATTERY_CLASS "battery" @@ -19,5 +20,6 @@ struct acpi_battery_hook { void battery_hook_register(struct acpi_battery_hook *hook); void battery_hook_unregister(struct acpi_battery_hook *hook); +int devm_battery_hook_register(struct device *dev, struct acpi_battery_hook *hook); #endif From c05cb5bdf413a2a5051701a397082380758e37ec Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Thomas=20Wei=C3=9Fschuh?= Date: Sun, 30 Jun 2024 22:54:09 +0200 Subject: [PATCH 23/28] platform/chrome: Update binary interface for EC-based charge control MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The charge-control command v2/v3 is more featureful than v1, it additionally supports charge thresholds. The definitions were imported from ChromeOS EC commit 32870d602317 ("squirtle: modify motionsense rotation matrix") Signed-off-by: Thomas Weißschuh Link: https://lore.kernel.org/r/20240630-cros_ec-charge-control-v5-2-8f649d018c52@weissschuh.net Signed-off-by: Tzung-Bi Shih --- .../linux/platform_data/cros_ec_commands.h | 49 ++++++++++++++++++- 1 file changed, 47 insertions(+), 2 deletions(-) diff --git a/include/linux/platform_data/cros_ec_commands.h b/include/linux/platform_data/cros_ec_commands.h index ec598057d1dab5..e574b790be6fbc 100644 --- a/include/linux/platform_data/cros_ec_commands.h +++ b/include/linux/platform_data/cros_ec_commands.h @@ -3843,16 +3843,61 @@ struct ec_params_i2c_write { * discharge the battery. */ #define EC_CMD_CHARGE_CONTROL 0x0096 -#define EC_VER_CHARGE_CONTROL 1 +#define EC_VER_CHARGE_CONTROL 3 enum ec_charge_control_mode { CHARGE_CONTROL_NORMAL = 0, CHARGE_CONTROL_IDLE, CHARGE_CONTROL_DISCHARGE, + /* Add no more entry below. */ + CHARGE_CONTROL_COUNT, +}; + +#define EC_CHARGE_MODE_TEXT \ + { \ + [CHARGE_CONTROL_NORMAL] = "NORMAL", \ + [CHARGE_CONTROL_IDLE] = "IDLE", \ + [CHARGE_CONTROL_DISCHARGE] = "DISCHARGE", \ + } + +enum ec_charge_control_cmd { + EC_CHARGE_CONTROL_CMD_SET = 0, + EC_CHARGE_CONTROL_CMD_GET, +}; + +enum ec_charge_control_flag { + EC_CHARGE_CONTROL_FLAG_NO_IDLE = BIT(0), }; struct ec_params_charge_control { - uint32_t mode; /* enum charge_control_mode */ + uint32_t mode; /* enum charge_control_mode */ + + /* Below are the fields added in V2. */ + uint8_t cmd; /* enum ec_charge_control_cmd. */ + uint8_t flags; /* enum ec_charge_control_flag (v3+) */ + /* + * Lower and upper thresholds for battery sustainer. This struct isn't + * named to avoid tainting foreign projects' name spaces. + * + * If charge mode is explicitly set (e.g. DISCHARGE), battery sustainer + * will be disabled. To disable battery sustainer, set mode=NORMAL, + * lower=-1, upper=-1. + */ + struct { + int8_t lower; /* Display SoC in percentage. */ + int8_t upper; /* Display SoC in percentage. */ + } sustain_soc; +} __ec_align4; + +/* Added in v2 */ +struct ec_response_charge_control { + uint32_t mode; /* enum charge_control_mode */ + struct { /* Battery sustainer thresholds */ + int8_t lower; + int8_t upper; + } sustain_soc; + uint8_t flags; /* enum ec_charge_control_flag (v3+) */ + uint8_t reserved; } __ec_align4; /*****************************************************************************/ From 69a13742b7c64ed89894caf7091539e164b3e97c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Thomas=20Wei=C3=9Fschuh?= Date: Sun, 30 Jun 2024 22:54:10 +0200 Subject: [PATCH 24/28] platform/chrome: cros_ec_proto: Introduce cros_ec_get_cmd_versions() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Retrieving the supported versions of a command is a fairly common operation. Provide a helper for it. If the command is not supported at all the EC returns -EINVAL/EC_RES_INVALID_PARAMS. This error is translated into an empty version mask as that is easier to handle for callers and they don't need to know about the error details. Signed-off-by: Thomas Weißschuh Link: https://lore.kernel.org/r/20240630-cros_ec-charge-control-v5-3-8f649d018c52@weissschuh.net Signed-off-by: Tzung-Bi Shih --- drivers/platform/chrome/cros_ec_proto.c | 35 +++++++++++++++++++++ include/linux/platform_data/cros_ec_proto.h | 2 ++ 2 files changed, 37 insertions(+) diff --git a/drivers/platform/chrome/cros_ec_proto.c b/drivers/platform/chrome/cros_ec_proto.c index fe68be66ee988d..f776fd42244f4c 100644 --- a/drivers/platform/chrome/cros_ec_proto.c +++ b/drivers/platform/chrome/cros_ec_proto.c @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -1069,3 +1070,37 @@ int cros_ec_cmd_readmem(struct cros_ec_device *ec_dev, u8 offset, u8 size, void ¶ms, sizeof(params), dest, size); } EXPORT_SYMBOL_GPL(cros_ec_cmd_readmem); + +/** + * cros_ec_get_cmd_versions - Get supported version mask. + * + * @ec_dev: EC device + * @cmd: Command to test + * + * Return: version mask on success, negative error number on failure. + */ +int cros_ec_get_cmd_versions(struct cros_ec_device *ec_dev, u16 cmd) +{ + struct ec_params_get_cmd_versions req_v0; + struct ec_params_get_cmd_versions_v1 req_v1; + struct ec_response_get_cmd_versions resp; + int ret; + + if (cmd <= U8_MAX) { + req_v0.cmd = cmd; + ret = cros_ec_cmd(ec_dev, 0, EC_CMD_GET_CMD_VERSIONS, + &req_v0, sizeof(req_v0), &resp, sizeof(resp)); + } else { + req_v1.cmd = cmd; + ret = cros_ec_cmd(ec_dev, 1, EC_CMD_GET_CMD_VERSIONS, + &req_v1, sizeof(req_v1), &resp, sizeof(resp)); + } + + if (ret == -EINVAL) + return 0; /* Command not implemented */ + else if (ret < 0) + return ret; + else + return resp.version_mask; +} +EXPORT_SYMBOL_GPL(cros_ec_get_cmd_versions); diff --git a/include/linux/platform_data/cros_ec_proto.h b/include/linux/platform_data/cros_ec_proto.h index 6e9225bdf903d1..b34ed0cc1f8dc8 100644 --- a/include/linux/platform_data/cros_ec_proto.h +++ b/include/linux/platform_data/cros_ec_proto.h @@ -263,6 +263,8 @@ int cros_ec_cmd(struct cros_ec_device *ec_dev, unsigned int version, int command int cros_ec_cmd_readmem(struct cros_ec_device *ec_dev, u8 offset, u8 size, void *dest); +int cros_ec_get_cmd_versions(struct cros_ec_device *ec_dev, u16 cmd); + /** * cros_ec_get_time_ns() - Return time in ns. * From c6ed48ef52599098498a8442fd60bea5bd8cd309 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Thomas=20Wei=C3=9Fschuh?= Date: Sun, 30 Jun 2024 22:54:11 +0200 Subject: [PATCH 25/28] power: supply: add ChromeOS EC based charge control driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The ChromeOS Embedded Controller implements a command to control charge thresholds and behaviour. Use it to implement the standard Linux charge_control_start_threshold, charge_control_end_threshold and charge_behaviour sysfs UAPIs. The driver is designed to be probed via the cros_ec mfd device. Acked-by: Sebastian Reichel Signed-off-by: Thomas Weißschuh Link: https://lore.kernel.org/r/20240630-cros_ec-charge-control-v5-4-8f649d018c52@weissschuh.net Signed-off-by: Tzung-Bi Shih --- MAINTAINERS | 6 + drivers/power/supply/Kconfig | 12 + drivers/power/supply/Makefile | 1 + drivers/power/supply/cros_charge-control.c | 332 +++++++++++++++++++++ 4 files changed, 351 insertions(+) create mode 100644 drivers/power/supply/cros_charge-control.c diff --git a/MAINTAINERS b/MAINTAINERS index e4e6aad46668b5..8101cd0df305f4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -5135,6 +5135,11 @@ S: Maintained F: Documentation/devicetree/bindings/sound/google,cros-ec-codec.yaml F: sound/soc/codecs/cros_ec_codec.* +CHROMEOS EC CHARGE CONTROL +M: Thomas Weißschuh +S: Maintained +F: drivers/power/supply/cros_charge-control.c + CHROMEOS EC HARDWARE MONITORING M: Thomas Weißschuh L: chrome-platform@lists.linux.dev @@ -5148,6 +5153,7 @@ M: Benson Leung R: Guenter Roeck L: chrome-platform@lists.linux.dev S: Maintained +F: drivers/power/supply/cros_charge-control.c F: drivers/power/supply/cros_usbpd-charger.c N: cros_ec N: cros-ec diff --git a/drivers/power/supply/Kconfig b/drivers/power/supply/Kconfig index 3e31375491d580..f6321a42aa5331 100644 --- a/drivers/power/supply/Kconfig +++ b/drivers/power/supply/Kconfig @@ -860,6 +860,18 @@ config CHARGER_CROS_PCHG the peripheral charge ports from the EC and converts that into power_supply properties. +config CHARGER_CROS_CONTROL + tristate "ChromeOS EC based charge control" + depends on MFD_CROS_EC_DEV + depends on ACPI_BATTERY + default MFD_CROS_EC_DEV + help + Say Y here to enable ChromeOS EC based battery charge control. + This driver can manage charge thresholds and behaviour. + + This driver can also be built as a module. If so, the module will be + called cros_charge-control. + config CHARGER_SC2731 tristate "Spreadtrum SC2731 charger driver" depends on MFD_SC27XX_PMIC || COMPILE_TEST diff --git a/drivers/power/supply/Makefile b/drivers/power/supply/Makefile index 58b56727803498..31ca6653a564cd 100644 --- a/drivers/power/supply/Makefile +++ b/drivers/power/supply/Makefile @@ -100,6 +100,7 @@ obj-$(CONFIG_CHARGER_TPS65090) += tps65090-charger.o obj-$(CONFIG_CHARGER_TPS65217) += tps65217_charger.o obj-$(CONFIG_AXP288_FUEL_GAUGE) += axp288_fuel_gauge.o obj-$(CONFIG_AXP288_CHARGER) += axp288_charger.o +obj-$(CONFIG_CHARGER_CROS_CONTROL) += cros_charge-control.o obj-$(CONFIG_CHARGER_CROS_USBPD) += cros_usbpd-charger.o obj-$(CONFIG_CHARGER_CROS_PCHG) += cros_peripheral_charger.o obj-$(CONFIG_CHARGER_SC2731) += sc2731_charger.o diff --git a/drivers/power/supply/cros_charge-control.c b/drivers/power/supply/cros_charge-control.c new file mode 100644 index 00000000000000..521b0eb4ff3b20 --- /dev/null +++ b/drivers/power/supply/cros_charge-control.c @@ -0,0 +1,332 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * ChromeOS EC driver for charge control + * + * Copyright (C) 2024 Thomas Weißschuh + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#define EC_CHARGE_CONTROL_BEHAVIOURS (BIT(POWER_SUPPLY_CHARGE_BEHAVIOUR_AUTO) | \ + BIT(POWER_SUPPLY_CHARGE_BEHAVIOUR_INHIBIT_CHARGE) | \ + BIT(POWER_SUPPLY_CHARGE_BEHAVIOUR_FORCE_DISCHARGE)) + +enum CROS_CHCTL_ATTR { + CROS_CHCTL_ATTR_START_THRESHOLD, + CROS_CHCTL_ATTR_END_THRESHOLD, + CROS_CHCTL_ATTR_CHARGE_BEHAVIOUR, + _CROS_CHCTL_ATTR_COUNT +}; + +/* + * Semantics of data *returned* from the EC API and Linux sysfs differ + * slightly, also the v1 API can not return any data. + * To match the expected sysfs API, data is never read back from the EC but + * cached in the driver. + * + * Changes to the EC bypassing the driver will not be reflected in sysfs. + * Any change to "charge_behaviour" will synchronize the EC with the driver state. + */ + +struct cros_chctl_priv { + struct cros_ec_device *cros_ec; + struct acpi_battery_hook battery_hook; + struct power_supply *hooked_battery; + u8 cmd_version; + + /* The callbacks need to access this priv structure. + * As neither the struct device nor power_supply are under the drivers + * control, embed the attributes within priv to use with container_of(). + */ + struct device_attribute device_attrs[_CROS_CHCTL_ATTR_COUNT]; + struct attribute *attributes[_CROS_CHCTL_ATTR_COUNT]; + struct attribute_group group; + + enum power_supply_charge_behaviour current_behaviour; + u8 current_start_threshold, current_end_threshold; +}; + +static int cros_chctl_send_charge_control_cmd(struct cros_ec_device *cros_ec, + u8 cmd_version, struct ec_params_charge_control *req) +{ + static const u8 outsizes[] = { + [1] = offsetof(struct ec_params_charge_control, cmd), + [2] = sizeof(struct ec_params_charge_control), + [3] = sizeof(struct ec_params_charge_control), + }; + + struct { + struct cros_ec_command msg; + union { + struct ec_params_charge_control req; + struct ec_response_charge_control resp; + } __packed data; + } __packed buf = { + .msg = { + .command = EC_CMD_CHARGE_CONTROL, + .version = cmd_version, + .insize = 0, + .outsize = outsizes[cmd_version], + }, + .data.req = *req, + }; + + return cros_ec_cmd_xfer_status(cros_ec, &buf.msg); +} + +static int cros_chctl_configure_ec(struct cros_chctl_priv *priv) +{ + struct ec_params_charge_control req = {}; + + req.cmd = EC_CHARGE_CONTROL_CMD_SET; + + switch (priv->current_behaviour) { + case POWER_SUPPLY_CHARGE_BEHAVIOUR_AUTO: + req.mode = CHARGE_CONTROL_NORMAL; + break; + case POWER_SUPPLY_CHARGE_BEHAVIOUR_INHIBIT_CHARGE: + req.mode = CHARGE_CONTROL_IDLE; + break; + case POWER_SUPPLY_CHARGE_BEHAVIOUR_FORCE_DISCHARGE: + req.mode = CHARGE_CONTROL_DISCHARGE; + break; + default: + return -EINVAL; + } + + if (priv->current_behaviour == POWER_SUPPLY_CHARGE_BEHAVIOUR_AUTO && + !(priv->current_start_threshold == 0 && priv->current_end_threshold == 100)) { + req.sustain_soc.lower = priv->current_start_threshold; + req.sustain_soc.upper = priv->current_end_threshold; + } else { + /* Disable charging limits */ + req.sustain_soc.lower = -1; + req.sustain_soc.upper = -1; + } + + return cros_chctl_send_charge_control_cmd(priv->cros_ec, priv->cmd_version, &req); +} + +static struct cros_chctl_priv *cros_chctl_attr_to_priv(struct attribute *attr, + enum CROS_CHCTL_ATTR idx) +{ + struct device_attribute *dev_attr = container_of(attr, struct device_attribute, attr); + + return container_of(dev_attr, struct cros_chctl_priv, device_attrs[idx]); +} + +static ssize_t cros_chctl_store_threshold(struct device *dev, struct cros_chctl_priv *priv, + int is_end_threshold, const char *buf, size_t count) +{ + int ret, val; + + ret = kstrtoint(buf, 10, &val); + if (ret < 0) + return ret; + if (val < 0 || val > 100) + return -EINVAL; + + if (is_end_threshold) { + if (val <= priv->current_start_threshold) + return -EINVAL; + priv->current_end_threshold = val; + } else { + if (val >= priv->current_end_threshold) + return -EINVAL; + priv->current_start_threshold = val; + } + + if (priv->current_behaviour == POWER_SUPPLY_CHARGE_BEHAVIOUR_AUTO) { + ret = cros_chctl_configure_ec(priv); + if (ret < 0) + return ret; + } + + return count; +} + +static ssize_t charge_control_start_threshold_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct cros_chctl_priv *priv = cros_chctl_attr_to_priv(&attr->attr, + CROS_CHCTL_ATTR_START_THRESHOLD); + + return sysfs_emit(buf, "%u\n", (unsigned int)priv->current_start_threshold); +} + +static ssize_t charge_control_start_threshold_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct cros_chctl_priv *priv = cros_chctl_attr_to_priv(&attr->attr, + CROS_CHCTL_ATTR_START_THRESHOLD); + + return cros_chctl_store_threshold(dev, priv, 0, buf, count); +} + +static ssize_t charge_control_end_threshold_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct cros_chctl_priv *priv = cros_chctl_attr_to_priv(&attr->attr, + CROS_CHCTL_ATTR_END_THRESHOLD); + + return sysfs_emit(buf, "%u\n", (unsigned int)priv->current_end_threshold); +} + +static ssize_t charge_control_end_threshold_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + struct cros_chctl_priv *priv = cros_chctl_attr_to_priv(&attr->attr, + CROS_CHCTL_ATTR_END_THRESHOLD); + + return cros_chctl_store_threshold(dev, priv, 1, buf, count); +} + +static ssize_t charge_behaviour_show(struct device *dev, struct device_attribute *attr, char *buf) +{ + struct cros_chctl_priv *priv = cros_chctl_attr_to_priv(&attr->attr, + CROS_CHCTL_ATTR_CHARGE_BEHAVIOUR); + + return power_supply_charge_behaviour_show(dev, EC_CHARGE_CONTROL_BEHAVIOURS, + priv->current_behaviour, buf); +} + +static ssize_t charge_behaviour_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + struct cros_chctl_priv *priv = cros_chctl_attr_to_priv(&attr->attr, + CROS_CHCTL_ATTR_CHARGE_BEHAVIOUR); + enum power_supply_charge_behaviour behaviour; + int ret; + + behaviour = power_supply_charge_behaviour_parse(EC_CHARGE_CONTROL_BEHAVIOURS, buf); + if (behaviour < 0) + return behaviour; + + priv->current_behaviour = behaviour; + + ret = cros_chctl_configure_ec(priv); + if (ret < 0) + return ret; + + return count; +} + +static umode_t cros_chtl_attr_is_visible(struct kobject *kobj, struct attribute *attr, int n) +{ + struct cros_chctl_priv *priv = cros_chctl_attr_to_priv(attr, n); + + if (priv->cmd_version < 2) { + if (n == CROS_CHCTL_ATTR_START_THRESHOLD) + return 0; + if (n == CROS_CHCTL_ATTR_END_THRESHOLD) + return 0; + } + + return attr->mode; +} + +static int cros_chctl_add_battery(struct power_supply *battery, struct acpi_battery_hook *hook) +{ + struct cros_chctl_priv *priv = container_of(hook, struct cros_chctl_priv, battery_hook); + + if (priv->hooked_battery) + return 0; + + priv->hooked_battery = battery; + return device_add_group(&battery->dev, &priv->group); +} + +static int cros_chctl_remove_battery(struct power_supply *battery, struct acpi_battery_hook *hook) +{ + struct cros_chctl_priv *priv = container_of(hook, struct cros_chctl_priv, battery_hook); + + if (priv->hooked_battery == battery) { + device_remove_group(&battery->dev, &priv->group); + priv->hooked_battery = NULL; + } + + return 0; +} + +static int cros_chctl_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct cros_ec_dev *ec_dev = dev_get_drvdata(dev->parent); + struct cros_ec_device *cros_ec = ec_dev->ec_dev; + struct cros_chctl_priv *priv; + size_t i; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + ret = cros_ec_get_cmd_versions(cros_ec, EC_CMD_CHARGE_CONTROL); + if (ret < 0) + return ret; + else if (ret & EC_VER_MASK(3)) + priv->cmd_version = 3; + else if (ret & EC_VER_MASK(2)) + priv->cmd_version = 2; + else if (ret & EC_VER_MASK(1)) + priv->cmd_version = 1; + else + return -ENODEV; + + dev_dbg(dev, "Command version: %u\n", (unsigned int)priv->cmd_version); + + priv->cros_ec = cros_ec; + priv->device_attrs[CROS_CHCTL_ATTR_START_THRESHOLD] = + (struct device_attribute)__ATTR_RW(charge_control_start_threshold); + priv->device_attrs[CROS_CHCTL_ATTR_END_THRESHOLD] = + (struct device_attribute)__ATTR_RW(charge_control_end_threshold); + priv->device_attrs[CROS_CHCTL_ATTR_CHARGE_BEHAVIOUR] = + (struct device_attribute)__ATTR_RW(charge_behaviour); + for (i = 0; i < _CROS_CHCTL_ATTR_COUNT; i++) { + sysfs_attr_init(&priv->device_attrs[i].attr); + priv->attributes[i] = &priv->device_attrs[i].attr; + } + priv->attributes[_CROS_CHCTL_ATTR_COUNT] = NULL; + priv->group.is_visible = cros_chtl_attr_is_visible; + priv->group.attrs = priv->attributes; + + priv->battery_hook.name = dev_name(dev); + priv->battery_hook.add_battery = cros_chctl_add_battery; + priv->battery_hook.remove_battery = cros_chctl_remove_battery; + + priv->current_behaviour = POWER_SUPPLY_CHARGE_BEHAVIOUR_AUTO; + priv->current_start_threshold = 0; + priv->current_end_threshold = 100; + + /* Bring EC into well-known state */ + ret = cros_chctl_configure_ec(priv); + if (ret < 0) + return ret; + + return devm_battery_hook_register(dev, &priv->battery_hook); +} + +static const struct platform_device_id cros_chctl_id[] = { + { "cros-charge-control", 0 }, + {} +}; + +static struct platform_driver cros_chctl_driver = { + .driver.name = "cros-charge-control", + .probe = cros_chctl_probe, + .id_table = cros_chctl_id, +}; +module_platform_driver(cros_chctl_driver); + +MODULE_DEVICE_TABLE(platform, cros_chctl_id); +MODULE_DESCRIPTION("ChromeOS EC charge control"); +MODULE_AUTHOR("Thomas Weißschuh "); +MODULE_LICENSE("GPL"); From 3664706e875f84bd4e3fa25ed1c6e46934cb32cd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Thomas=20Wei=C3=9Fschuh?= Date: Sun, 30 Jun 2024 22:54:12 +0200 Subject: [PATCH 26/28] power: supply: cros_charge-control: don't load if Framework control is present MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Framework laptops implement a custom charge control EC command. The upstream CrOS EC command is also present and functional but can get overridden by the custom one. Until Framework make both commands compatible or remove their custom one, don't load the driver on those machines. If the user knows they are not going to use the custom command they can use a module parameter to load cros_charge-control anyways. Note that the UEFI setup configuration for battery control also uses their custom command. Signed-off-by: Thomas Weißschuh Link: https://lore.kernel.org/r/20240630-cros_ec-charge-control-v5-5-8f649d018c52@weissschuh.net Signed-off-by: Tzung-Bi Shih --- drivers/power/supply/cros_charge-control.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/power/supply/cros_charge-control.c b/drivers/power/supply/cros_charge-control.c index 521b0eb4ff3b20..73d7f2dc0fa34e 100644 --- a/drivers/power/supply/cros_charge-control.c +++ b/drivers/power/supply/cros_charge-control.c @@ -6,6 +6,7 @@ */ #include #include +#include #include #include #include @@ -256,6 +257,19 @@ static int cros_chctl_remove_battery(struct power_supply *battery, struct acpi_b return 0; } +static bool probe_with_fwk_charge_control; +module_param(probe_with_fwk_charge_control, bool, 0644); +MODULE_PARM_DESC(probe_with_fwk_charge_control, + "Probe the driver in the presence of the custom Framework EC charge control"); + +static int cros_chctl_fwk_charge_control_versions(struct cros_ec_device *cros_ec) +{ + if (!dmi_match(DMI_SYS_VENDOR, "Framework")) + return 0; + + return cros_ec_get_cmd_versions(cros_ec, 0x3E03 /* FW_EC_CMD_CHARGE_LIMIT */); +} + static int cros_chctl_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -265,6 +279,14 @@ static int cros_chctl_probe(struct platform_device *pdev) size_t i; int ret; + ret = cros_chctl_fwk_charge_control_versions(cros_ec); + if (ret < 0) + return ret; + if (ret > 0 && !probe_with_fwk_charge_control) { + dev_info(dev, "Framework charge control detected, preventing load\n"); + return -ENODEV; + } + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); if (!priv) return -ENOMEM; From c98f17fec35e46629272226a898ebb0a653ee270 Mon Sep 17 00:00:00 2001 From: Nathan Chancellor Date: Tue, 2 Jul 2024 07:48:48 -0700 Subject: [PATCH 27/28] power: supply: cros_charge-control: Avoid accessing attributes out of bounds MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Clang warns (or errors with CONFIG_WERROR=y): drivers/power/supply/cros_charge-control.c:319:2: error: array index 3 is past the end of the array (that has type 'struct attribute *[3]') [-Werror,-Warray-bounds] 319 | priv->attributes[_CROS_CHCTL_ATTR_COUNT] = NULL; | ^ ~~~~~~~~~~~~~~~~~~~~~~ drivers/power/supply/cros_charge-control.c:49:2: note: array 'attributes' declared here 49 | struct attribute *attributes[_CROS_CHCTL_ATTR_COUNT]; | ^ 1 error generated. In earlier revisions of the driver, the attributes array in cros_chctl_priv had four elements with four distinct assignments but during review, the number of elements was changed to three through use of an enum and the assignments became a for loop, except for this one, which is now out of bounds. This assignment is no longer necessary because the size of the attributes array no longer accounts for it, so just remove it to clear up the warning. Fixes: c6ed48ef5259 ("power: supply: add ChromeOS EC based charge control driver") Signed-off-by: Nathan Chancellor Acked-by: Thomas Weißschuh Link: https://lore.kernel.org/r/20240702-cros_charge-control-fix-clang-array-bounds-warning-v1-1-ae04d995cd1d@kernel.org Signed-off-by: Tzung-Bi Shih --- drivers/power/supply/cros_charge-control.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/power/supply/cros_charge-control.c b/drivers/power/supply/cros_charge-control.c index 73d7f2dc0fa34e..2dd8ddbd56bc09 100644 --- a/drivers/power/supply/cros_charge-control.c +++ b/drivers/power/supply/cros_charge-control.c @@ -316,7 +316,6 @@ static int cros_chctl_probe(struct platform_device *pdev) sysfs_attr_init(&priv->device_attrs[i].attr); priv->attributes[i] = &priv->device_attrs[i].attr; } - priv->attributes[_CROS_CHCTL_ATTR_COUNT] = NULL; priv->group.is_visible = cros_chtl_attr_is_visible; priv->group.attrs = priv->attributes; From 4baf1cc54433ff7c6e5178517bc8768001416681 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Thu, 4 Jul 2024 10:20:03 -0500 Subject: [PATCH 28/28] power: supply: cros_charge-control: Fix signedness bug in charge_behaviour_store() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The C standard is vague about the signedness of enums, but in this case here, they are treated as unsigned so the error handling does not work. Use an int type to fix this. Fixes: c6ed48ef5259 ("power: supply: add ChromeOS EC based charge control driver") Signed-off-by: Dan Carpenter Acked-by: Thomas Weißschuh Link: https://lore.kernel.org/r/ZoWKEs4mCqeLyTOB@stanley.mountain Signed-off-by: Tzung-Bi Shih --- drivers/power/supply/cros_charge-control.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/power/supply/cros_charge-control.c b/drivers/power/supply/cros_charge-control.c index 2dd8ddbd56bc09..17c53591ce197d 100644 --- a/drivers/power/supply/cros_charge-control.c +++ b/drivers/power/supply/cros_charge-control.c @@ -204,14 +204,13 @@ static ssize_t charge_behaviour_store(struct device *dev, struct device_attribut { struct cros_chctl_priv *priv = cros_chctl_attr_to_priv(&attr->attr, CROS_CHCTL_ATTR_CHARGE_BEHAVIOUR); - enum power_supply_charge_behaviour behaviour; int ret; - behaviour = power_supply_charge_behaviour_parse(EC_CHARGE_CONTROL_BEHAVIOURS, buf); - if (behaviour < 0) - return behaviour; + ret = power_supply_charge_behaviour_parse(EC_CHARGE_CONTROL_BEHAVIOURS, buf); + if (ret < 0) + return ret; - priv->current_behaviour = behaviour; + priv->current_behaviour = ret; ret = cros_chctl_configure_ec(priv); if (ret < 0)