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StanfordArm.mdl
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StanfordArm.mdl
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CPPClassGenCompliant off
AutosarCompliant off
UseMalloc off
ExtMode off
ExtModeStaticAlloc off
ExtModeTesting off
ExtModeStaticAllocSize 1000000
ExtModeTransport 0
ExtModeMexFile "ext_comm"
ExtModeIntrfLevel "Level1"
RTWCAPISignals off
RTWCAPIParams off
RTWCAPIStates off
GenerateASAP2 off
}
PropName "Components"
}
}
hdlcoderui.hdlcc {
$ObjectID 13
Version "1.10.0"
Description "HDL Coder custom configuration component"
Name "HDL Coder"
Array {
Type "Cell"
Dimension 1
Cell ""
PropName "HDLConfigFile"
}
HDLCActiveTab "0"
}
PropName "Components"
}
Name "Configuration"
CurrentDlgPage "Solver"
ConfigPrmDlgPosition " [ 0, 0, 861, 561 ] "
}
PropName "ConfigurationSets"
}
Simulink.ConfigSet {
$PropName "ActiveConfigurationSet"
$ObjectID 2
}
BlockDefaults {
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
NamePlacement "normal"
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
ShowName on
BlockRotation 0
BlockMirror off
}
AnnotationDefaults {
HorizontalAlignment "center"
VerticalAlignment "middle"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
UseDisplayTextAsClickCallback off
}
LineDefaults {
FontName "Helvetica"
FontSize 9
FontWeight "normal"
FontAngle "normal"
}
BlockParameterDefaults {
Block {
BlockType Demux
Outputs "4"
DisplayOption "none"
BusSelectionMode off
}
Block {
BlockType Inport
Port "1"
OutMin "[]"
OutMax "[]"
OutDataTypeStr "Inherit: auto"
LockScale off
BusOutputAsStruct off
PortDimensions "-1"
VarSizeSig "Inherit"
SampleTime "-1"
SignalType "auto"
SamplingMode "auto"
LatchByDelayingOutsideSignal off
LatchInputForFeedbackSignals off
Interpolate on
}
Block {
BlockType Integrator
ExternalReset "none"
InitialConditionSource "internal"
InitialCondition "0"
LimitOutput off
UpperSaturationLimit "inf"
LowerSaturationLimit "-inf"
ShowSaturationPort off
ShowStatePort off
AbsoluteTolerance "auto"
IgnoreLimit off
ZeroCross on
ContinuousStateAttributes "''"
}
Block {
BlockType Mux
Inputs "4"
DisplayOption "none"
UseBusObject off
BusObject "BusObject"
NonVirtualBus off
}
Block {
BlockType Outport
Port "1"
OutMin "[]"
OutMax "[]"
OutDataTypeStr "Inherit: auto"
LockScale off
BusOutputAsStruct off
PortDimensions "-1"
VarSizeSig "Inherit"
SampleTime "-1"
SignalType "auto"
SamplingMode "auto"
SourceOfInitialOutputValue "Dialog"
OutputWhenDisabled "held"
InitialOutput "[]"
}
Block {
BlockType "S-Function"
FunctionName "system"
SFunctionModules "''"
PortCounts "[]"
SFunctionDeploymentMode off
}
Block {
BlockType Saturate
UpperLimitSource "Dialog"
UpperLimit "0.5"
LowerLimitSource "Dialog"
LowerLimit "-0.5"
LinearizeAsGain on
ZeroCross on
SampleTime "-1"
OutMin "[]"
OutMax "[]"
OutDataTypeStr "Inherit: Same as input"
LockScale off
RndMeth "Floor"
}
Block {
BlockType Step
Time "1"
Before "0"
After "1"
SampleTime "-1"
VectorParams1D on
ZeroCross on
}
Block {
BlockType SubSystem
ShowPortLabels "FromPortIcon"
Permissions "ReadWrite"
PermitHierarchicalResolution "All"
TreatAsAtomicUnit off
CheckFcnCallInpInsideContextMsg off
SystemSampleTime "-1"
RTWFcnNameOpts "Auto"
RTWFileNameOpts "Auto"
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
SimViewingDevice off
DataTypeOverride "UseLocalSettings"
DataTypeOverrideAppliesTo "AllNumericTypes"
MinMaxOverflowLogging "UseLocalSettings"
Variant off
GeneratePreprocessorConditionals off
}
Block {
BlockType Terminator
}
}
System {
Name "StanfordArm"
Location [625, 281, 1373, 632]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
ReportName "simulink-default.rpt"
SIDHighWatermark "56"
Block {
BlockType SubSystem
Name "Embedded\nMATLAB Function"
SID "46"
Ports [1, 1]
Position [145, 77, 215, 123]
LibraryVersion "1.31"
PermitHierarchicalResolution "ExplicitOnly"
TreatAsAtomicUnit on
MinAlgLoopOccurrences off
PropExecContextOutsideSubsystem off
RTWSystemCode "Auto"
FunctionWithSeparateData off
Opaque off
Array {
Type "Handle"
Dimension 0
PropName "AvailSigsLoadSave"
}
RequestExecContextInheritance off
MaskHideContents off
MaskType "Stateflow"
MaskDescription "Embedded MATLAB block"
MaskSelfModifiable on
MaskDisplay "disp('fcn');"
MaskIconFrame on
MaskIconOpaque off
MaskIconRotate "none"
MaskPortRotate "default"
MaskIconUnits "autoscale"
System {
Name "Embedded\nMATLAB Function"
Location [257, 457, 812, 717]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
SIDHighWatermark "17"
Block {
BlockType Inport
Name "f"
SID "46::1"
Position [20, 101, 40, 119]
IconDisplay "Port number"
}
Block {
BlockType Demux
Name " Demux "
SID "46::15"
Ports [1, 1]
Position [270, 160, 320, 200]
Outputs "1"
}
Block {
BlockType "S-Function"
Name " SFunction "
SID "46::14"
Tag "Stateflow S-Function StanfordArm 2"
Ports [1, 2]
Position [180, 100, 230, 160]
FunctionName "sf_sfun"
PortCounts "[1 2]"
EnableBusSupport on
Port {
PortNumber 2
Name "qdd"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
}
Block {
BlockType Terminator
Name " Terminator "
SID "46::17"
Position [460, 171, 480, 189]
}
Block {
BlockType Outport
Name "qdd"
SID "46::5"
Position [460, 101, 480, 119]
IconDisplay "Port number"
}
Line {
SrcBlock " SFunction "
SrcPort 1
DstBlock " Demux "
DstPort 1
}
Line {
SrcBlock "f"
SrcPort 1
DstBlock " SFunction "
DstPort 1
}
Line {
Name "qdd"
Labels [0, 0]
SrcBlock " SFunction "
SrcPort 2
DstBlock "qdd"
DstPort 1
}
Line {
SrcBlock " Demux "
SrcPort 1
DstBlock " Terminator "
DstPort 1
}
}
}
Block {
BlockType Integrator
Name "Integrator"
SID "49"
Ports [1, 1]
Position [365, 85, 395, 115]
}
Block {
BlockType Integrator
Name "Integrator1"
SID "50"
Ports [1, 1]
Position [260, 85, 290, 115]
}
Block {
BlockType Mux
Name "Mux"
SID "47"
Ports [2, 1]
Position [110, 81, 115, 119]
ShowName off
Inputs "2"
DisplayOption "bar"
}
Block {
BlockType Saturate
Name "Saturation"
SID "52"
Ports [1, 1]
Position [445, 85, 475, 115]
InputPortMap "u0"
UpperLimit "2"
LowerLimit "-2"
}
Block {
BlockType Step
Name "Step"
SID "56"
Position [30, 75, 60, 105]
After "-1"
SampleTime "0"
}
Block {
BlockType Reference
Name "T2xyz"
SID "53"
Ports [1, 3]
Position [605, 152, 655, 208]
BackgroundColor "red"
LibraryVersion "1.26"
SourceBlock "roblocks/T2xyz"
SourceType ""
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
GeneratePreprocessorConditionals off
}
Block {
BlockType Reference
Name "XY Graph"
SID "54"
Ports [2]
Position [700, 156, 730, 189]
LibraryVersion "1.225"
SourceBlock "simulink/Sinks/XY Graph"
SourceType "XY scope."
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
GeneratePreprocessorConditionals off
xmin "-2"
xmax "2"
ymin "-2"
ymax "2"
st "-1"
}
Block {
BlockType Reference
Name "fkine"
SID "55"
Ports [1, 1]
Position [510, 152, 560, 208]
BackgroundColor "red"
LibraryVersion "1.26"
SourceBlock "roblocks/fkine"
SourceType ""
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"