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adi_regmap_adc_v9.xml
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adi_regmap_adc_v9.xml
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<!-- -->
<!-- Copyright (C) 2014-2015 Analog Devices, Inc. -->
<!-- This is a machine generated file, do not modify -->
<!-- Please send bug reports to http://ez.analog.com/community/fpga -->
<!-- -->
<adi_regmap_adc>
<Register>
<Name>REG_VERSION</Name>
<Address>0x0000</Address>
<Description>Version and Scratch Registers (REG_VERSION)</Description>
<Exists>True</Exists>
<Width>32</Width>
<Notes></Notes>
<BitFields>
<BitField>
<Name>VERSION[31:0]</Name>
<Access>RO</Access>
<Description>VERSION[31:0]</Description>
<Visibility>Public</Visibility>
<Width>32</Width>
<Notes>Version number.</Notes>
<BitOffset>0</BitOffset>
<RegOffset>0</RegOffset>
<SliceWidth>32</SliceWidth>
</BitField>
</BitFields>
</Register>
<Register>
<Name>REG_ID</Name>
<Address>0x0004</Address>
<Description>Version and Scratch Registers (REG_ID)</Description>
<Exists>True</Exists>
<Width>32</Width>
<Notes></Notes>
<BitFields>
<BitField>
<Name>ID[31:0]</Name>
<Access>RO</Access>
<Description>ID[31:0]</Description>
<Visibility>Public</Visibility>
<Width>32</Width>
<Notes>Instance identifier number.</Notes>
<BitOffset>0</BitOffset>
<RegOffset>0</RegOffset>
<SliceWidth>32</SliceWidth>
</BitField>
</BitFields>
</Register>
<Register>
<Name>REG_SCRATCH</Name>
<Address>0x0008</Address>
<Description>Version and Scratch Registers (REG_SCRATCH)</Description>
<Exists>True</Exists>
<Width>32</Width>
<Notes></Notes>
<BitFields>
<BitField>
<Name>SCRATCH[31:0]</Name>
<Access>RW</Access>
<Description>SCRATCH[31:0]</Description>
<Visibility>Public</Visibility>
<Width>32</Width>
<Notes>Scratch register.</Notes>
<BitOffset>0</BitOffset>
<RegOffset>0</RegOffset>
<SliceWidth>32</SliceWidth>
</BitField>
</BitFields>
</Register>
<Register>
<Name>REG_RSTN</Name>
<Address>0x0040</Address>
<Description>ADC Interface Control & Status (REG_RSTN)</Description>
<Exists>True</Exists>
<Width>32</Width>
<Notes></Notes>
<BitFields>
<BitField>
<Name>MMCM_RSTN</Name>
<Access>RW</Access>
<Description>MMCM_RSTN</Description>
<Visibility>Public</Visibility>
<Width>1</Width>
<Notes>MMCM reset only (required for DRP access). Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.</Notes>
<BitOffset>0</BitOffset>
<RegOffset>1</RegOffset>
<SliceWidth>1</SliceWidth>
</BitField>
<BitField>
<Name>RSTN</Name>
<Access>RW</Access>
<Description>RSTN</Description>
<Visibility>Public</Visibility>
<Width>1</Width>
<Notes>Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.</Notes>
<BitOffset>0</BitOffset>
<RegOffset>0</RegOffset>
<SliceWidth>1</SliceWidth>
</BitField>
</BitFields>
</Register>
<Register>
<Name>REG_CNTRL</Name>
<Address>0x0044</Address>
<Description>ADC Interface Control & Status (REG_CNTRL)</Description>
<Exists>True</Exists>
<Width>32</Width>
<Notes></Notes>
<BitFields>
<BitField>
<Name>R1_MODE</Name>
<Access>RW</Access>
<Description>R1_MODE</Description>
<Visibility>Public</Visibility>
<Width>1</Width>
<Notes>Select number of RF channels 1 (0x1) or 2 (0x0).</Notes>
<BitOffset>0</BitOffset>
<RegOffset>2</RegOffset>
<SliceWidth>1</SliceWidth>
</BitField>
<BitField>
<Name>DDR_EDGESEL</Name>
<Access>RW</Access>
<Description>DDR_EDGESEL</Description>
<Visibility>Public</Visibility>
<Width>1</Width>
<Notes>Select rising edge (0x0) or falling edge (0x1) for the first part of a sample (if applicable) followed by the successive edges for the remaining parts. This only controls how the sample is delineated from the incoming data post DDR registers.</Notes>
<BitOffset>0</BitOffset>
<RegOffset>1</RegOffset>
<SliceWidth>1</SliceWidth>
</BitField>
<BitField>
<Name>PIN_MODE</Name>
<Access>RW</Access>
<Description>PIN_MODE</Description>
<Visibility>Public</Visibility>
<Width>1</Width>
<Notes>Select interface pin mode to be clock multiplexed (0x1) or pin multiplexed (0x0). In clock multiplexed mode, samples are received on alternative clock edges. In pin multiplexed mode, samples are interleaved or grouped on the pins at the same clock edge.</Notes>
<BitOffset>0</BitOffset>
<RegOffset>0</RegOffset>
<SliceWidth>1</SliceWidth>
</BitField>
</BitFields>
</Register>
<Register>
<Name>REG_CLK_FREQ</Name>
<Address>0x0054</Address>
<Description>ADC Interface Control & Status (REG_CLK_FREQ)</Description>
<Exists>True</Exists>
<Width>32</Width>
<Notes></Notes>
<BitFields>
<BitField>
<Name>CLK_FREQ[31:0]</Name>
<Access>RO</Access>
<Description>CLK_FREQ[31:0]</Description>
<Visibility>Public</Visibility>
<Width>32</Width>
<Notes>Interface clock frequency. This is relative to the processor clock and in many cases is 100MHz. The number is represented as unsigned 16.16 format. Assuming a 100MHz processor clock the minimum is 1.523kHz and maximum is 6.554THz. The actual interface clock is CLK_FREQ * CLK_RATIO (see below). Note that the actual sampling clock may not be the same as the interface clock- software must consider device specific implementation parameters to calculate the final sampling clock.</Notes>
<BitOffset>0</BitOffset>
<RegOffset>0</RegOffset>
<SliceWidth>32</SliceWidth>
</BitField>
</BitFields>
</Register>
<Register>
<Name>REG_CLK_RATIO</Name>
<Address>0x0058</Address>
<Description>ADC Interface Control & Status (REG_CLK_RATIO)</Description>
<Exists>True</Exists>
<Width>32</Width>
<Notes></Notes>
<BitFields>
<BitField>
<Name>CLK_RATIO[31:0]</Name>
<Access>RO</Access>
<Description>CLK_RATIO[31:0]</Description>
<Visibility>Public</Visibility>
<Width>32</Width>
<Notes>Interface clock ratio - as a factor actual received clock. This is implementation specific and depends on any serial to parallel conversion and interface type (ddr/sdr/qdr).</Notes>
<BitOffset>0</BitOffset>
<RegOffset>0</RegOffset>
<SliceWidth>32</SliceWidth>
</BitField>
</BitFields>
</Register>
<Register>
<Name>REG_STATUS</Name>
<Address>0x005C</Address>
<Description>ADC Interface Control & Status (REG_STATUS)</Description>
<Exists>True</Exists>
<Width>32</Width>
<Notes></Notes>
<BitFields>
<BitField>
<Name>PN_ERR</Name>
<Access>RO</Access>
<Description>PN_ERR</Description>
<Visibility>Public</Visibility>
<Width>1</Width>
<Notes>If set, indicates pn error in one or more channels.</Notes>
<BitOffset>0</BitOffset>
<RegOffset>3</RegOffset>
<SliceWidth>1</SliceWidth>
</BitField>
<BitField>
<Name>PN_OOS</Name>
<Access>RO</Access>
<Description>PN_OOS</Description>
<Visibility>Public</Visibility>
<Width>1</Width>
<Notes>If set, indicates pn oos in one or more channels.</Notes>
<BitOffset>0</BitOffset>
<RegOffset>2</RegOffset>
<SliceWidth>1</SliceWidth>
</BitField>
<BitField>
<Name>OVER_RANGE</Name>
<Access>RO</Access>
<Description>OVER_RANGE</Description>
<Visibility>Public</Visibility>
<Width>1</Width>
<Notes>If set, indicates over range in one or more channels.</Notes>
<BitOffset>0</BitOffset>
<RegOffset>1</RegOffset>
<SliceWidth>1</SliceWidth>
</BitField>
<BitField>
<Name>STATUS</Name>
<Access>RO</Access>
<Description>STATUS</Description>
<Visibility>Public</Visibility>
<Width>1</Width>
<Notes>Interface status, if set indicates no errors. If not set, there are errors, software may try resetting the cores.</Notes>
<BitOffset>0</BitOffset>
<RegOffset>0</RegOffset>
<SliceWidth>1</SliceWidth>
</BitField>
</BitFields>
</Register>
<Register>
<Name>REG_DELAY_CNTRL</Name>
<Address>0x0060</Address>
<Description>ADC Interface Control & Status (REG_DELAY_CNTRL)</Description>
<Exists>True</Exists>
<Width>32</Width>
<Notes></Notes>
<BitFields>
<BitField>
<Name>DELAY_SEL</Name>
<Access>RW</Access>
<Description>DELAY_SEL</Description>
<Visibility>Public</Visibility>
<Width>1</Width>
<Notes>Delay select, a 0x0 to 0x1 transition in this register initiates a delay access controlled by the registers below.</Notes>
<BitOffset>0</BitOffset>
<RegOffset>17</RegOffset>
<SliceWidth>1</SliceWidth>
</BitField>
<BitField>
<Name>DELAY_RWN</Name>
<Access>RW</Access>
<Description>DELAY_RWN</Description>
<Visibility>Public</Visibility>
<Width>1</Width>
<Notes>Delay read (0x1) or write (0x0), the delay is accessed directly (no increment or decrement) with an address corresponding to each pin, and data corresponding to the total delay.</Notes>
<BitOffset>0</BitOffset>
<RegOffset>16</RegOffset>
<SliceWidth>1</SliceWidth>
</BitField>
<BitField>
<Name>DELAY_ADDRESS[7:0]</Name>
<Access>RW</Access>
<Description>DELAY_ADDRESS[7:0]</Description>
<Visibility>Public</Visibility>
<Width>8</Width>
<Notes>Delay address, the range depends on the interface pins, data pins are usually at the lower range.</Notes>
<BitOffset>0</BitOffset>
<RegOffset>8</RegOffset>
<SliceWidth>8</SliceWidth>
</BitField>
<BitField>
<Name>DELAY_WDATA[4:0]</Name>
<Access>RW</Access>
<Description>DELAY_WDATA[4:0]</Description>
<Visibility>Public</Visibility>
<Width>5</Width>
<Notes>Delay write data, a value of 1 corresponds to (1/200)ns for most devices.</Notes>
<BitOffset>0</BitOffset>
<RegOffset>0</RegOffset>
<SliceWidth>5</SliceWidth>
</BitField>
</BitFields>
</Register>
<Register>
<Name>REG_DELAY_STATUS</Name>
<Address>0x0064</Address>
<Description>ADC Interface Control & Status (REG_DELAY_STATUS)</Description>
<Exists>True</Exists>
<Width>32</Width>
<Notes></Notes>
<BitFields>
<BitField>
<Name>DELAY_LOCKED</Name>
<Access>RO</Access>
<Description>DELAY_LOCKED</Description>
<Visibility>Public</Visibility>
<Width>1</Width>
<Notes>Indicates delay locked (0x1) state. If this bit is read 0x0, delay control has failed to calibrate the elements.</Notes>
<BitOffset>0</BitOffset>
<RegOffset>9</RegOffset>
<SliceWidth>1</SliceWidth>
</BitField>
<BitField>
<Name>DELAY_STATUS</Name>
<Access>RO</Access>
<Description>DELAY_STATUS</Description>
<Visibility>Public</Visibility>
<Width>1</Width>
<Notes>If set, indicates busy status (access pending). The read data may not be valid if this bit is set.</Notes>
<BitOffset>0</BitOffset>
<RegOffset>8</RegOffset>
<SliceWidth>1</SliceWidth>
</BitField>
<BitField>
<Name>DELAY_RDATA[4:0]</Name>
<Access>RO</Access>
<Description>DELAY_RDATA[4:0]</Description>
<Visibility>Public</Visibility>
<Width>5</Width>
<Notes>Delay read data, current delay value in the elements</Notes>
<BitOffset>0</BitOffset>
<RegOffset>0</RegOffset>
<SliceWidth>5</SliceWidth>
</BitField>
</BitFields>
</Register>
<Register>
<Name>REG_DRP_CNTRL</Name>
<Address>0x0070</Address>
<Description>ADC Interface Control & Status (REG_DRP_CNTRL)</Description>
<Exists>True</Exists>
<Width>32</Width>
<Notes></Notes>
<BitFields>
<BitField>
<Name>DRP_RWN</Name>
<Access>RW</Access>
<Description>DRP_RWN</Description>
<Visibility>Public</Visibility>
<Width>1</Width>
<Notes>DRP read (0x1) or write (0x0) select (does not include GTX lanes).</Notes>
<BitOffset>0</BitOffset>
<RegOffset>28</RegOffset>
<SliceWidth>1</SliceWidth>
</BitField>
<BitField>
<Name>DRP_ADDRESS[11:0]</Name>
<Access>RW</Access>
<Description>DRP_ADDRESS[11:0]</Description>
<Visibility>Public</Visibility>
<Width>12</Width>
<Notes>DRP address, designs that contain more than one DRP accessible primitives have selects based on the most significant bits (does not include GTX lanes).</Notes>
<BitOffset>0</BitOffset>
<RegOffset>16</RegOffset>
<SliceWidth>12</SliceWidth>
</BitField>
<BitField>
<Name>DRP_WDATA[15:0]</Name>
<Access>RW</Access>
<Description>DRP_WDATA[15:0]</Description>
<Visibility>Public</Visibility>
<Width>16</Width>
<Notes>DRP write data (does not include GTX lanes).</Notes>
<BitOffset>0</BitOffset>
<RegOffset>0</RegOffset>
<SliceWidth>16</SliceWidth>
</BitField>
</BitFields>
</Register>
<Register>
<Name>REG_DRP_STATUS</Name>
<Address>0x0074</Address>
<Description>ADC Interface Control & Status (REG_DRP_STATUS)</Description>
<Exists>True</Exists>
<Width>32</Width>
<Notes></Notes>
<BitFields>
<BitField>
<Name>DRP_STATUS</Name>
<Access>RO</Access>
<Description>DRP_STATUS</Description>
<Visibility>Public</Visibility>
<Width>1</Width>
<Notes>If set indicates busy (access pending). The read data may not be valid if this bit is set (does not include GTX lanes).</Notes>
<BitOffset>0</BitOffset>
<RegOffset>16</RegOffset>
<SliceWidth>1</SliceWidth>
</BitField>
<BitField>
<Name>DRP_RDATA</Name>
<Access>RO</Access>
<Description>DRP_RDATA</Description>
<Visibility>Public</Visibility>
<Width>16</Width>
<Notes>DRP read data (does not include GTX lanes).</Notes>
<BitOffset>0</BitOffset>
<RegOffset>0</RegOffset>
<SliceWidth>16</SliceWidth>
</BitField>
</BitFields>
</Register>
<Register>
<Name>REG_UI_STATUS</Name>
<Address>0x0088</Address>
<Description>User Interface Status (REG_UI_STATUS)</Description>
<Exists>True</Exists>
<Width>32</Width>
<Notes></Notes>
<BitFields>
<BitField>
<Name>UI_OVF</Name>
<Access>RW1C</Access>
<Description>UI_OVF</Description>
<Visibility>Public</Visibility>
<Width>1</Width>
<Notes>User Interface overflow. If set, indicates an overflow occurred during data transfer at the user interface (FIFO interface). Software must write a 0x1 to clear this register bit.</Notes>
<BitOffset>0</BitOffset>
<RegOffset>2</RegOffset>
<SliceWidth>1</SliceWidth>
</BitField>
<BitField>
<Name>UI_UNF</Name>
<Access>RW1C</Access>
<Description>UI_UNF</Description>
<Visibility>Public</Visibility>
<Width>1</Width>
<Notes>User Interface underflow. If set, indicates an underflow occurred during data transfer at the user interface (FIFO interface). Software must write a 0x1 to clear this register bit.</Notes>
<BitOffset>0</BitOffset>
<RegOffset>1</RegOffset>
<SliceWidth>1</SliceWidth>
</BitField>
<BitField>
<Name>UI_RESERVED</Name>
<Access>RW1C</Access>
<Description>UI_RESERVED</Description>
<Visibility>Public</Visibility>
<Width>1</Width>
<Notes>Reserved for backward compatibility.</Notes>
<BitOffset>0</BitOffset>
<RegOffset>0</RegOffset>
<SliceWidth>1</SliceWidth>
</BitField>
</BitFields>
</Register>
<Register>
<Name>REG_USR_CNTRL_1</Name>
<Address>0x00A0</Address>
<Description>ADC Interface Control & Status (REG_USR_CNTRL_1)</Description>
<Exists>True</Exists>
<Width>32</Width>
<Notes></Notes>
<BitFields>
<BitField>
<Name>USR_CHANMAX[7:0]</Name>
<Access>RW</Access>
<Description>USR_CHANMAX[7:0]</Description>
<Visibility>Public</Visibility>
<Width>8</Width>
<Notes>This indicates the maximum number of inputs for the channel data multiplexers. User may add different processing modules post data capture as another input to this common multiplexer. NOT-APPLICABLE if ADC_DP_DISABLE is set (0x1).</Notes>
<BitOffset>0</BitOffset>
<RegOffset>0</RegOffset>
<SliceWidth>8</SliceWidth>
</BitField>
</BitFields>
</Register>
<Register>
<Name>REG_USR_CNTRL_1</Name>
<Address>0x00C0</Address>
<Description>ADC Interface Control & Status (REG_USR_CNTRL_1)</Description>
<Exists>True</Exists>
<Width>32</Width>
<Notes></Notes>
<BitFields>
<BitField>
<Name>ADC_DP_DISABLE</Name>
<Access>RO</Access>
<Description>ADC_DP_DISABLE</Description>
<Visibility>Public</Visibility>
<Width>1</Width>
<Notes>This indicates the data path disable setting of this pcore. If disabled, most of the HDL data path modules are disabled allowing an external core full access to the raw ADC data.</Notes>
<BitOffset>0</BitOffset>
<RegOffset>0</RegOffset>
<SliceWidth>1</SliceWidth>
</BitField>
</BitFields>
</Register>
<Register>
<Name>REG_CHAN_CNTRL</Name>
<Address>0x0400</Address>
<Description>ADC Interface Control & Status (REG_CHAN_CNTRL)</Description>
<Exists>True</Exists>
<Width>32</Width>
<Notes></Notes>
<BitFields>
<BitField>
<Name>RESERVED</Name>
<Access>RW</Access>
<Description>RESERVED</Description>
<Visibility>Public</Visibility>
<Width>1</Width>
<Notes>RESERVED</Notes>
<BitOffset>0</BitOffset>
<RegOffset>11</RegOffset>
<SliceWidth>1</SliceWidth>
</BitField>
<BitField>
<Name>RESERVED</Name>
<Access>RW</Access>
<Description>RESERVED</Description>
<Visibility>Public</Visibility>
<Width>1</Width>
<Notes>RESERVED</Notes>
<BitOffset>0</BitOffset>
<RegOffset>10</RegOffset>
<SliceWidth>1</SliceWidth>
</BitField>
<BitField>
<Name>IQCOR_ENB</Name>
<Access>RW</Access>
<Description>IQCOR_ENB</Description>
<Visibility>Public</Visibility>
<Width>1</Width>
<Notes>if set, enables IQ correction. NOT-APPLICABLE if ADC_DP_DISABLE is set (0x1).</Notes>
<BitOffset>0</BitOffset>
<RegOffset>9</RegOffset>
<SliceWidth>1</SliceWidth>
</BitField>
<BitField>
<Name>DCFILT_ENB</Name>
<Access>RW</Access>
<Description>DCFILT_ENB</Description>
<Visibility>Public</Visibility>
<Width>1</Width>
<Notes>if set, enables DC filter (to disable DC offset, set offset value to 0x0). NOT-APPLICABLE if ADC_DP_DISABLE is set (0x1).</Notes>
<BitOffset>0</BitOffset>
<RegOffset>8</RegOffset>
<SliceWidth>1</SliceWidth>
</BitField>
<BitField>
<Name>FORMAT_SIGNEXT</Name>
<Access>RW</Access>
<Description>FORMAT_SIGNEXT</Description>
<Visibility>Public</Visibility>
<Width>1</Width>
<Notes>if set, enables sign extension (applicable only in 2's complement mode). The data is always sign extended to the nearest byte boundary. NOT-APPLICABLE if ADC_DP_DISABLE is set (0x1).</Notes>
<BitOffset>0</BitOffset>
<RegOffset>6</RegOffset>
<SliceWidth>1</SliceWidth>
</BitField>
<BitField>
<Name>FORMAT_TYPE</Name>
<Access>RW</Access>
<Description>FORMAT_TYPE</Description>
<Visibility>Public</Visibility>
<Width>1</Width>
<Notes>Select offset binary (0x1) or 2's complement (0x0) data type. This sets the incoming data type and is required by the post processing modules for any data conversion. NOT-APPLICABLE if ADC_DP_DISABLE is set (0x1).</Notes>
<BitOffset>0</BitOffset>
<RegOffset>5</RegOffset>
<SliceWidth>1</SliceWidth>
</BitField>
<BitField>
<Name>FORMAT_ENABLE</Name>
<Access>RW</Access>
<Description>FORMAT_ENABLE</Description>
<Visibility>Public</Visibility>
<Width>1</Width>
<Notes>Enable data format conversion (see register bits above). NOT-APPLICABLE if ADC_DP_DISABLE is set (0x1).</Notes>
<BitOffset>0</BitOffset>
<RegOffset>4</RegOffset>
<SliceWidth>1</SliceWidth>
</BitField>
<BitField>
<Name>RESERVED</Name>
<Access>RW</Access>
<Description>RESERVED</Description>
<Visibility>Public</Visibility>
<Width>1</Width>
<Notes>RESERVED</Notes>
<BitOffset>0</BitOffset>
<RegOffset>1</RegOffset>
<SliceWidth>1</SliceWidth>
</BitField>
<BitField>
<Name>ENABLE</Name>
<Access>RW</Access>
<Description>ENABLE</Description>
<Visibility>Public</Visibility>
<Width>1</Width>
<Notes>If set, enables channel. A 0x0 to 0x1 transition transfers all the control signals to the respective channel processing module. If a channel is part of a complex signal (I/Q), even channel is the master and the odd channel is the slave. Though a single control is used, both must be individually selected. NOT-APPLICABLE if ADC_DP_DISABLE is set (0x1).</Notes>
<BitOffset>0</BitOffset>
<RegOffset>0</RegOffset>
<SliceWidth>1</SliceWidth>
</BitField>
</BitFields>
</Register>
<Register>
<Name>REG_CHAN_STATUS</Name>
<Address>0x0404</Address>
<Description>ADC Interface Control & Status (REG_CHAN_STATUS)</Description>
<Exists>True</Exists>
<Width>32</Width>
<Notes></Notes>
<BitFields>
<BitField>
<Name>PN_ERR</Name>
<Access>RW1C</Access>
<Description>PN_ERR</Description>
<Visibility>Public</Visibility>
<Width>1</Width>
<Notes>PN errors. If set, indicates spurious mismatches in sync state. This bit is cleared if OOS is set and is only indicates errors when OOS is cleared.</Notes>
<BitOffset>0</BitOffset>
<RegOffset>2</RegOffset>
<SliceWidth>1</SliceWidth>
</BitField>
<BitField>
<Name>PN_OOS</Name>
<Access>RW1C</Access>
<Description>PN_OOS</Description>
<Visibility>Public</Visibility>
<Width>1</Width>
<Notes>PN Out Of Sync. If set, indicates an OOS status. OOS is set, if 64 consecutive patterns mismatch from the expected pattern. It is cleared, when 16 consecutive patterns match the expected pattern.</Notes>
<BitOffset>0</BitOffset>
<RegOffset>1</RegOffset>
<SliceWidth>1</SliceWidth>
</BitField>
<BitField>
<Name>OVER_RANGE</Name>
<Access>RW1C</Access>
<Description>OVER_RANGE</Description>
<Visibility>Public</Visibility>
<Width>1</Width>
<Notes>If set, indicates over range. Note that over range is independent of the data path, it indicates an over range over a data transfer period. Software must first clear this bit before initiating a transfer and monitor afterwards.</Notes>
<BitOffset>0</BitOffset>
<RegOffset>0</RegOffset>
<SliceWidth>1</SliceWidth>
</BitField>
</BitFields>
</Register>
<Register>
<Name>REG_CHAN_CNTRL_1</Name>
<Address>0x0410</Address>
<Description>ADC Interface Control & Status (REG_CHAN_CNTRL_1)</Description>
<Exists>True</Exists>
<Width>32</Width>
<Notes></Notes>
<BitFields>
<BitField>
<Name>DCFILT_OFFSET[15:0]</Name>
<Access>RW</Access>
<Description>DCFILT_OFFSET[15:0]</Description>
<Visibility>Public</Visibility>
<Width>16</Width>
<Notes>DC removal (if equipped) offset. This is a 2's complement number added to the incoming data to remove a known DC offset. NOT-APPLICABLE if ADC_DP_DISABLE is set (0x1).</Notes>
<BitOffset>0</BitOffset>
<RegOffset>16</RegOffset>
<SliceWidth>16</SliceWidth>
</BitField>
<BitField>
<Name>DCFILT_COEFF[15:0]</Name>
<Access>RW</Access>
<Description>DCFILT_COEFF[15:0]</Description>
<Visibility>Public</Visibility>
<Width>16</Width>
<Notes>DC removal filter (if equipped) coefficient. The format is 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if ADC_DP_DISABLE is set (0x1).</Notes>
<BitOffset>0</BitOffset>
<RegOffset>0</RegOffset>
<SliceWidth>16</SliceWidth>
</BitField>
</BitFields>
</Register>
<Register>
<Name>REG_CHAN_CNTRL_2</Name>
<Address>0x0414</Address>
<Description>ADC Interface Control & Status (REG_CHAN_CNTRL_2)</Description>
<Exists>True</Exists>
<Width>32</Width>
<Notes></Notes>
<BitFields>
<BitField>
<Name>IQCOR_COEFF_1[15:0]</Name>
<Access>RW</Access>
<Description>IQCOR_COEFF_1[15:0]</Description>
<Visibility>Public</Visibility>
<Width>16</Width>
<Notes>IQ correction (if equipped) coefficient. If scale & offset is implemented, this is the scale value and the format is 1.1.14 (sign, integer and fractional bits). If matrix multiplication is used, this is the channel I coefficient and the format is 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if ADC_DP_DISABLE is set (0x1).</Notes>
<BitOffset>0</BitOffset>
<RegOffset>16</RegOffset>
<SliceWidth>16</SliceWidth>
</BitField>
<BitField>
<Name>IQCOR_COEFF_2[15:0]</Name>
<Access>RW</Access>
<Description>IQCOR_COEFF_2[15:0]</Description>
<Visibility>Public</Visibility>
<Width>16</Width>
<Notes>IQ correction (if equipped) coefficient. If scale & offset is implemented, this is the offset value and the format is 2's complement. If matrix multiplication is used, this is the channel Q coefficient and the format is 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if ADC_DP_DISABLE is set (0x1).</Notes>
<BitOffset>0</BitOffset>
<RegOffset>0</RegOffset>
<SliceWidth>16</SliceWidth>
</BitField>
</BitFields>
</Register>
<Register>
<Name>REG_CHAN_CNTRL_3</Name>
<Address>0x0418</Address>
<Description>ADC Interface Control & Status (REG_CHAN_CNTRL_3)</Description>
<Exists>True</Exists>
<Width>32</Width>
<Notes></Notes>
<BitFields>
<BitField>
<Name>ADC_PN_SEL[3:0]</Name>
<Access>RW</Access>
<Description>ADC_PN_SEL[3:0]</Description>
<Visibility>Public</Visibility>
<Width>4</Width>
<Notes>Selects the PN monitor sequence type (available only if ADC supports it). 0x0: pn9a (device specific, modified pn9) 0x1: pn23a (device specific, modified pn23) 0x4: pn7 (standard O.150) 0x5: pn15 (standard O.150) 0x6: pn23 (standard O.150) 0x7: pn31 (standard O.150) 0x9: pnX (device specific, e.g. ad9361)</Notes>
<BitOffset>0</BitOffset>
<RegOffset>16</RegOffset>
<SliceWidth>4</SliceWidth>
</BitField>
<BitField>
<Name>ADC_DATA_SEL[3:0]</Name>
<Access>RW</Access>
<Description>ADC_DATA_SEL[3:0]</Description>
<Visibility>Public</Visibility>
<Width>4</Width>
<Notes>Selects the data source to DMA. 0x0: input data (ADC) 0x1: loopback data (DAC)</Notes>
<BitOffset>0</BitOffset>
<RegOffset>0</RegOffset>
<SliceWidth>4</SliceWidth>
</BitField>
</BitFields>
</Register>
<Register>
<Name>REG_CHAN_USR_CNTRL_1</Name>
<Address>0x0420</Address>
<Description>ADC Interface Control & Status (REG_CHAN_USR_CNTRL_1)</Description>
<Exists>True</Exists>
<Width>32</Width>
<Notes></Notes>
<BitFields>
<BitField>
<Name>USR_DATATYPE_BE</Name>
<Access>RW</Access>
<Description>USR_DATATYPE_BE</Description>
<Visibility>Public</Visibility>
<Width>1</Width>
<Notes>The user data type format- if set, indicates big endian (default is little endian). NOT-APPLICABLE if ADC_DP_DISABLE is set (0x1).</Notes>
<BitOffset>0</BitOffset>
<RegOffset>25</RegOffset>
<SliceWidth>1</SliceWidth>
</BitField>
<BitField>
<Name>USR_DATATYPE_SIGNED</Name>
<Access>RW</Access>
<Description>USR_DATATYPE_SIGNED</Description>
<Visibility>Public</Visibility>
<Width>1</Width>
<Notes>The user data type format- if set, indicates signed (2's complement) data (default is unsigned). NOT-APPLICABLE if ADC_DP_DISABLE is set (0x1).</Notes>
<BitOffset>0</BitOffset>
<RegOffset>24</RegOffset>
<SliceWidth>1</SliceWidth>
</BitField>
<BitField>
<Name>USR_DATATYPE_SHIFT[7:0]</Name>
<Access>RW</Access>
<Description>USR_DATATYPE_SHIFT[7:0]</Description>
<Visibility>Public</Visibility>
<Width>8</Width>
<Notes>The user data type format- the amount of right shift for actual samples within the total number of bits. NOT-APPLICABLE if ADC_DP_DISABLE is set (0x1).</Notes>
<BitOffset>0</BitOffset>
<RegOffset>16</RegOffset>
<SliceWidth>8</SliceWidth>
</BitField>
<BitField>
<Name>USR_DATATYPE_TOTAL_BITS[7:0]</Name>
<Access>RW</Access>
<Description>USR_DATATYPE_TOTAL_BITS[7:0]</Description>
<Visibility>Public</Visibility>
<Width>8</Width>
<Notes>The user data type format- number of total bits used for a sample. The total number of bits must be an integer multiple of 8 (byte aligned). NOT-APPLICABLE if ADC_DP_DISABLE is set (0x1).</Notes>
<BitOffset>0</BitOffset>
<RegOffset>8</RegOffset>
<SliceWidth>8</SliceWidth>
</BitField>
<BitField>
<Name>USR_DATATYPE_BITS[7:0]</Name>
<Access>RW</Access>
<Description>USR_DATATYPE_BITS[7:0]</Description>
<Visibility>Public</Visibility>
<Width>8</Width>
<Notes>The user data type format- number of bits in a sample. This indicates the actual sample data bits. NOT-APPLICABLE if ADC_DP_DISABLE is set (0x1).</Notes>
<BitOffset>0</BitOffset>
<RegOffset>0</RegOffset>
<SliceWidth>8</SliceWidth>
</BitField>
</BitFields>
</Register>
<Register>
<Name>REG_CHAN_USR_CNTRL_2</Name>
<Address>0x0424</Address>
<Description>ADC Interface Control & Status (REG_CHAN_USR_CNTRL_2)</Description>
<Exists>True</Exists>
<Width>32</Width>
<Notes></Notes>
<BitFields>
<BitField>
<Name>USR_DECIMATION_M[15:0]</Name>
<Access>RW</Access>
<Description>USR_DECIMATION_M[15:0]</Description>
<Visibility>Public</Visibility>
<Width>16</Width>
<Notes>This holds the user decimation M value of the channel that is currently being selected on the multiplexer above. The total decimation factor is of the form M/N. NOT-APPLICABLE if ADC_DP_DISABLE is set (0x1).</Notes>
<BitOffset>0</BitOffset>
<RegOffset>16</RegOffset>
<SliceWidth>16</SliceWidth>
</BitField>
<BitField>
<Name>USR_DECIMATION_N[15:0]</Name>
<Access>RW</Access>
<Description>USR_DECIMATION_N[15:0]</Description>
<Visibility>Public</Visibility>
<Width>16</Width>
<Notes>This holds the user decimation N value of the channel that is currently being selected on the multiplexer above. The total decimation factor is of the form M/N. NOT-APPLICABLE if ADC_DP_DISABLE is set (0x1).</Notes>
<BitOffset>0</BitOffset>
<RegOffset>0</RegOffset>
<SliceWidth>16</SliceWidth>
</BitField>
</BitFields>
</Register>
<Register>
<Name>REG_*</Name>
<Address>0x0440</Address>
<Description>Channel 1, similar to register 0x100 to 0x10f. (REG_*)</Description>
<Exists>True</Exists>
<Width>32</Width>
<Notes></Notes>
<BitFields>
</BitFields>
</Register>
<Register>
<Name>REG_*</Name>
<Address>0x0480</Address>
<Description>Channel 2, similar to register 0x100 to 0x10f. (REG_*)</Description>
<Exists>True</Exists>
<Width>32</Width>
<Notes></Notes>
<BitFields>
</BitFields>
</Register>
<Register>
<Name>REG_*</Name>
<Address>0x07C0</Address>
<Description>Channel 15, similar to register 0x100 to 0x10f. (REG_*)</Description>
<Exists>True</Exists>
<Width>32</Width>
<Notes></Notes>
<BitFields>
</BitFields>
</Register>
</adi_regmap_adc>