ad9144.xml

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<!-- Copyright (C) 2013-2014 Analog Devices, Inc.                    -->
<!-- This is a machine generated file, do not modify                 -->
<!-- Please send bug reports to http://ez.analog.com/community/fpga  -->
<!--                                                                 -->
<ad9144>
	<Register>
		<Name>SPI_IntfConfA</Name>
		<Address>0x0</Address>
		<Description>SPI_INTFCONFA</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>SoftReset</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>SOFTRESET</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Soft Reset.Setting this bit initiates a reset. This bit is auto-clearing after the soft reset is complete.</Notes>
				<Options>
					<Option>
						<Description>Assert soft reset.</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Deassert soft reset.</Description>
						<Value>0</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>LsbFirst</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>LSBFIRST</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>LSB First.When set, this bit causes input and output data to be oriented as LSB first. When this bit is clear, the data is oriented as MSB first.</Notes>
				<Options>
					<Option>
						<Description>Shift LSB in first</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Shift MSB in First</Description>
						<Value>0</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>1</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>AddrInc</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>ADDRINC</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Address Increment.When this bit is set, it causes incrementing, streaming addresses; otherwise, it generates descending addresses.</Notes>
				<Options>
					<Option>
						<Description>Streaming addresses are incremented.</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Streaming addresses are decremented.</Description>
						<Value>0</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>2</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>SdoActive</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>SDOACTIVE</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>SDO active</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>3</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>SdoActive_M</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>SDOACTIVE_M</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>SDO active (mirror)</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>4</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>AddrInc_M</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>ADDRINC_M</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Address increment (mirror)</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>5</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>LsbFirst_M</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>LSBFIRST_M</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>LSB first (mirror)</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>6</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>SoftReset_M</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>SOFTRESET_M</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Soft reset (mirror)</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>7</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>ChipType</Name>
		<Address>0x3</Address>
		<Description>CHIPTYPE</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>ChipType</Name>
				<Access>R</Access>
				<DefaultValue>4</DefaultValue>
				<Description>CHIPTYPE</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>The product type is "High Speed DAC", which is represented by a code of 0x04.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>ProdIdL</Name>
		<Address>0x4</Address>
		<Description>PRODIDL</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>ProdIdL</Name>
				<Access>R</Access>
				<DefaultValue>68</DefaultValue>
				<Description>PRODIDL</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Product identification low</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>ProdIdH</Name>
		<Address>0x5</Address>
		<Description>PRODIDH</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>ProdIdH</Name>
				<Access>R</Access>
				<DefaultValue>145</DefaultValue>
				<Description>PRODIDH</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Product identification high</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>ChipGrade</Name>
		<Address>0x6</Address>
		<Description>CHIPGRADE</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>DEV_REVISION</Name>
				<Access>R</Access>
				<DefaultValue>2</DefaultValue>
				<Description>DEV_REVISION</Description>
				<Visibility>Public</Visibility>
				<Width>4</Width>
				<Notes>Device revision</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>4</SliceWidth>
			</BitField>
			<BitField>
				<Name>PROD_GRADE</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>PROD_GRADE</Description>
				<Visibility>Public</Visibility>
				<Width>4</Width>
				<Notes>Product grade</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>4</RegOffset>
				<SliceWidth>4</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>SPI_PageIndx</Name>
		<Address>0x8</Address>
		<Description>SPI_PAGEINDX</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>PageIndx</Name>
				<Access>R/W</Access>
				<DefaultValue>3</DefaultValue>
				<Description>DUAL_PAGE</Description>
				<Visibility>Public</Visibility>
				<Width>2</Width>
				<Notes>Selects which dual DAC pair is accessed and written to when changing digital features, such as digital gain, DC offset, NCO FTW</Notes>
				<Options>
					<Option>
						<Description>Access neither Dual A or Dual B.</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Access Dual A only.</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Access Dual B only.</Description>
						<Value>2</Value>
					</Option>
					<Option>
						<Description>Access both Dual A and Dual B.</Description>
						<Value>3</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>2</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>PWRCNTRL0</Name>
		<Address>0x11</Address>
		<Description>PWRCNTRL0</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>pd_dacm</Name>
				<Access>R/W</Access>
				<DefaultValue>1</DefaultValue>
				<Description>POWER DOWN MASTER BIAS</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Power down DAC master bias.This bit powers down the DAC master bias. The bias cell provides currents and DAC full-scale adjustments to the four DACs. With the DAC master bias powered down, the DACs are inoperative.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>2</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>pd_dac_3</Name>
				<Access>R/W</Access>
				<DefaultValue>1</DefaultValue>
				<Description>POWER DOWN DAC3</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Power down Qchannel DAC 3.This bit powers down DAC3. The PCLK must be enabled (Register 0x1C6, Bit 1 set high) for power-down to be functional.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>3</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>pd_dac_2</Name>
				<Access>R/W</Access>
				<DefaultValue>1</DefaultValue>
				<Description>POWER DOWN DAC2</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Power down I-Channel DAC 2.This bit powers down DAC2. The PCLK must be enabled (Register 0x1C6, Bit 1 set high) for power-down to be functional.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>4</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>pd_dac_1</Name>
				<Access>R/W</Access>
				<DefaultValue>1</DefaultValue>
				<Description>POWER DOWN DAC1</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Power down Q-Channel DAC 1.The bits power-down DAC1. The PCLK must be enabled (Register 0x1C6, Bit 1 set high) for power-down to be functional.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>5</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>pd_dac_0</Name>
				<Access>R/W</Access>
				<DefaultValue>1</DefaultValue>
				<Description>POWER DOWN DAC0</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Power down I-Channel DAC 0.Bit 6 powers down DAC0. The PCLK must be enabled (Register 0x1c6, Bit 1 set to high) for power-down to be functional.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>6</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>pd_bg</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>PD_BG</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Reference power-down.Bit 7 powers down the band gap reference for the entire chip. Circuits are provided with bias currents only when the band gap is enabled.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>7</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>TXENMASK</Name>
		<Address>0x12</Address>
		<Description>TXENMASK</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>dacA_mask</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>DUALA_MASK</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Dual A DAC TXEN0 mask.With this bit set high, the analog power to both the DACs for Dual A can be disabled by setting Txen0 low. The direct power-down for this functional also works. With this bit set low, the analog power to both the DACs for Dual A are disabled only by using the power-down bit in Register 0x080.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>dacB_mask</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>DUALB_MASK</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Dual B DAC TXEN1 mask.With this bit set to high, the analog power to both DACs for Dual B can be disabled by setting Txen1 low. The direct power-down for this function also works. With this bit set low, the analog power to both the DACs for Dual B are disabled only by using the power-down bit in Register 0x080.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>1</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>PWRCNTRL3</Name>
		<Address>0x13</Address>
		<Description>PWRCNTRL3</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>spi_pa_ctrl</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>SPI_PROTECT</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>PDP on/off via SPI</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>2</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>ena_pa_ctrl_from_spi</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>SPI_PROTECT_OUT</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Control PDP enable via SPI</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>3</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>ena_pa_ctrl_from_txensm</Name>
				<Access>R/W</Access>
				<DefaultValue>1</DefaultValue>
				<Description>TX_PROTECT_OUT</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Control PDP enable from TXEN state machine</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>5</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>ena_pa_ctrl_from_paprot_err</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>PDP_PROTECT_OUT</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Control PDP enable from PDP block</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>6</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>GROUP_DLY</Name>
		<Address>0x14</Address>
		<Description>GROUP_DLY</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>COARSE_GROUP_DLY</Name>
				<Access>R/W</Access>
				<DefaultValue>8</DefaultValue>
				<Description>GROUP_DLY</Description>
				<Visibility>Public</Visibility>
				<Width>4</Width>
				<Notes>Coarse Group Delay Control.Coarse group delay. 0 = minimum delay. 15 = maximum delay. The range of the delay is -4 to +3 DAC clock periods, and the resolution is 1/2 DAC clock period.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>4</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>IRQEN_STATUSMODE0</Name>
		<Address>0x1F</Address>
		<Description>IRQEN_STATUSMODE0</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>EN_LaneFifoERR</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>IRQEN_SMODE_LANEFIFOERR</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Enable lane FIFO error detection.A lane FIFO error occurs when there is a full or empty condition on any of the FIFOs between the deserializer block and the core digital. An error on this FIFO requires a link disable and reenable to remove. The status of the lane FIFOs can be found in Register 0x30C, FIFO full, and Register 0x30D, FIFO empty.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>1</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>EN_SerPllLOCK</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>IRQEN_SMODE_SERPLLLOCK</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Enable SERDES PLL lock detection.When enabled, the SERPLLLOCK shows that the SERDES (JESD interface) PLL has reached a lock state.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>2</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>EN_SerPllLOST</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>IRQEN_SMODE_SERPLLLOST</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Enable SERDES PLL lost detection.When enabled, the SERPLLLOCK shows that the SERDES (JESD interface) PLL has dropped its lock state.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>3</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>EN_DacPllLOCK</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>IRQEN_SMODE_DACPLLLOCK</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Enable DAC PLL lock detection.When enabled, the DACPLLLOCK shows that the DAC (clock generation) PLL has reached a lock state.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>4</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>EN_DacPllLOST</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>IRQEN_SMODE_DACPLLLOST</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Enable DAC PLL lost detection.When enabled, the DACPLLLOCK shows that the DAC (clock generation) PLL has dropped its lock state.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>5</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>EN_CalFAIL</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>IRQEN_SMODE_CALFAIL</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Enable calibration fail detection.This interrupt trips if and when the DAC calibration fails.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>6</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>EN_CalPASS</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>IRQEN_SMODE_CALPASS</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Enable calibration pass detection.This interrupt trips if and when the DAC calibration passes.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>7</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>IRQEN_STATUSMODE1</Name>
		<Address>0x20</Address>
		<Description>IRQEN_STATUSMODE1</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>EN_PRBSI0</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>IRQEN_SMODE_PRBS0</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Enable PRBS real DAC A interrupt</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>EN_PRBSQ0</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>IRQEN_SMODE_PRBS1</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Enable PRBS image DAC A interrupt</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>1</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>EN_PRBSI1</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>IRQEN_SMODE_PRBS2</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Enable PRBS real DAC B interrupt</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>2</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>EN_PRBSQ1</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>IRQEN_SMODE_PRBS3</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Enable PRBS image DAC B interrupt</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>3</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>IRQEN_STATUSMODE2</Name>
		<Address>0x21</Address>
		<Description>IRQEN_STATUSMODE2</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>EN_REFtrip0</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>IRQEN_SMODE_SYNC_TRIP0</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Link A alignment trip</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>EN_REFwlim0</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>IRQEN_SMODE_SYNC_WLIM0</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Link A over/under threshold</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>1</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>EN_REFrota0</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>IRQEN_SMODE_SYNC_ROTATE0</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Link A alignment rotate</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>2</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>EN_REFlock0</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>IRQEN_SMODE_SYNC_LOCK0</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Link A alignment locked</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>3</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>EN_REFncoclr0</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>IRQEN_SMODE_NCO_ALIGN0</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Link A NCO clear tripped</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>4</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>EN_BLNKdone0</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>IRQEN_SMODE_BLNKDONE0</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Link A blanking done</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>5</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>EN_PAErr0</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>IRQEN_SMODE_PDPERR0</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Link A PDP error</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>7</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>IRQEN_STATUSMODE3</Name>
		<Address>0x22</Address>
		<Description>IRQEN_STATUSMODE3</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>EN_REFtrip1</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>IRQEN_SMODE_SYNC_TRIP1</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Link B alignment trip</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>EN_REFwlim1</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>IRQEN_SMODE_SYNC_WLIM1</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Link B over/under threshold</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>1</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>EN_REFrota1</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>IRQEN_SMODE_SYNC_ROTATE1</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Link B alignment rotate</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>2</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>EN_REFlock1</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>IRQEN_SMODE_SYNC_LOCK1</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Link B alignment locked</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>3</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>EN_REFncoclr1</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>IRQEN_SMODE_NCO_ALIGN1</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Link B NCO clear tripped</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>4</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>EN_BLNKdone1</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>IRQEN_SMODE_BLNKDONE1</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Link B blanking done</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>5</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>EN_PAErr1</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>IRQEN_SMODE_PDPERR1</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Link B PDP error</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>7</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>IRQ_STATUS0</Name>
		<Address>0x23</Address>
		<Description>IRQ_STATUS0</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>IRQ_LaneFifoERR</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>LANEFIFOERR</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Lane FIFO error</Notes>
				<Options>
					<Option>
						<Description>Lane FIFO error.</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Lane FIFO error.</Description>
						<Value>0</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>1</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>IRQ_SerPllLock</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>SERPLLLOCK</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>SERDES PLL lock</Notes>
				<Options>
					<Option>
						<Description>SERDES PLL lock.</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>SERDES PLL lock.</Description>
						<Value>0</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>2</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>IRQ_SerPllLost</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>SERPLLLOST</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>SERDES PLL lost</Notes>
				<Options>
					<Option>
						<Description>SERDES PLL lost.</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>SERDES PLL lost.</Description>
						<Value>0</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>3</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>IRQ_DacPllLock</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>DACPLLLOCK</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>DAC PLL lock</Notes>
				<Options>
					<Option>
						<Description>DAC PLL lock.</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>DAC PLL lock.</Description>
						<Value>0</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>4</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>IRQ_DacPllLost</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>DACPLLLOST</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>DAC PLL lost</Notes>
				<Options>
					<Option>
						<Description>DAC PLL lost.</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>DAC PLL lost.</Description>
						<Value>0</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>5</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>IRQ_CalFAIL</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>CALFAIL</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Calibration fail detection</Notes>
				<Options>
					<Option>
						<Description>Calibration fail servicing.</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Calibration fail not servicing.</Description>
						<Value>0</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>6</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>IRQ_CalPASS</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>CALPASS</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Calibration pass detection</Notes>
				<Options>
					<Option>
						<Description>Calibration pass servicing.</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Calibration pass not servicing.</Description>
						<Value>0</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>7</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>IRQ_STATUS1</Name>
		<Address>0x24</Address>
		<Description>IRQ_STATUS1</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>IRQ_PRBSI0</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>PRBS0</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>PRBS data check error DAC 0 real</Notes>
				<Options>
					<Option>
						<Description>Service PRBS I0.</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Service PRBS I0.</Description>
						<Value>0</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>IRQ_PRBSQ0</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>PRBS1</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>PRBS data check error DAC 0 image</Notes>
				<Options>
					<Option>
						<Description>Service PRBS Q0.</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Service PRBS Q0.</Description>
						<Value>0</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>1</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>IRQ_PRBSI1</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>PRBS2</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>PRBS data check error DAC 1 real</Notes>
				<Options>
					<Option>
						<Description>Service PRBS I1.</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Service PRBS I1.</Description>
						<Value>0</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>2</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>IRQ_PRBSQ1</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>PRBS3</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>PRBS data check error DAC 1 image</Notes>
				<Options>
					<Option>
						<Description>Service PRBS Q1.</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Service PRBS Q1.</Description>
						<Value>0</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>3</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>IRQ_STATUS2</Name>
		<Address>0x25</Address>
		<Description>IRQ_STATUS2</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>IRQ_REFtrip0</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>SYNC_TRIP0</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Link A alignment rotate</Notes>
				<Options>
					<Option>
						<Description>Trip interrupt occurs.</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Trip interrupt occurs.</Description>
						<Value>0</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>IRQ_REFwlim0</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>SYNC_WLIM0</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Link A alignment lock</Notes>
				<Options>
					<Option>
						<Description>Service over/under limit interrupt.</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Service over/under limit interrupt.</Description>
						<Value>0</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>1</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>IRQ_REFrota0</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>SYNC_ROTATE0</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Link A alignment trip</Notes>
				<Options>
					<Option>
						<Description>Rotate interrupt occurs.</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Rotate interrupt occurs.</Description>
						<Value>0</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>2</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>IRQ_REFlock0</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>SYNC_LOCK0</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Link A BIST done</Notes>
				<Options>
					<Option>
						<Description>Link A alignment locked.</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Link A alignment locked.</Description>
						<Value>0</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>3</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>IRQ_REFncoclr0</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>NCO_ALIGN0</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Link A alignment underrange</Notes>
				<Options>
					<Option>
						<Description>NCO clear tripped.</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>NCO clear tripped.</Description>
						<Value>0</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>4</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>IRQ_BLNKdone0</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>BLNKDONE0</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Link A blanking done</Notes>
				<Options>
					<Option>
						<Description>Link A blank done.</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Link A blank done.</Description>
						<Value>0</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>5</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>IRQ_PAErr0</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>PDPERR0</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Link A PDP error</Notes>
				<Options>
					<Option>
						<Description>Service Link A PDP error.</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Service LinkA PA Error</Description>
						<Value>0</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>7</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>IRQ_STATUS3</Name>
		<Address>0x26</Address>
		<Description>IRQ_STATUS3</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>IRQ_REFtrip1</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>SYNC_TRIP1</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Link B alignment rotate</Notes>
				<Options>
					<Option>
						<Description>REF trip.</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>REF trip.</Description>
						<Value>0</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>IRQ_REFwlim1</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>SYNC_WLIM1</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Link B alignment lock</Notes>
				<Options>
					<Option>
						<Description>Service over/under limit interrupt.</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Service over/under limit interrupt.</Description>
						<Value>0</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>1</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>IRQ_REFrota1</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>SYNC_ROTATE1</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Link B alignment trip</Notes>
				<Options>
					<Option>
						<Description>Rotate interrupt occurs.</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Rotate interrupt occurs.</Description>
						<Value>0</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>2</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>IRQ_REFlock1</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>SYNC_LOCK1</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Link B BIST done</Notes>
				<Options>
					<Option>
						<Description>Link B alignment locked.</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Link B alignment locked.</Description>
						<Value>0</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>3</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>IRQ_REFncoclr1</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>NCO_ALIGN1</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Link B alignment underrange</Notes>
				<Options>
					<Option>
						<Description>NCO clear tripped.</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>NCO clear tripped.</Description>
						<Value>0</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>4</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>IRQ_BLNKdone1</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>BLNKDONE1</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Link B blanking done</Notes>
				<Options>
					<Option>
						<Description>Link B blank done.</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Link B blank done.</Description>
						<Value>0</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>5</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>IRQ_PAErr1</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>PDPERR1</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Link B PDP error</Notes>
				<Options>
					<Option>
						<Description>Service Link B PDP error.</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Service Link B PDP error.</Description>
						<Value>0</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>7</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>JESD_CHECKS</Name>
		<Address>0x30</Address>
		<Description>JESD_CHECKS</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>ERR_INTsupp</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>ERR_INTSUPP</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Unsupported interpolation rate factor</Notes>
				<Options>
					<Option>
						<Description>Error with interpolation rate value.</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>No error with interpolation rate value.</Description>
						<Value>0</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>ERR_SubClass</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>ERR_SUBCLASS</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Unsupported subclass value</Notes>
				<Options>
					<Option>
						<Description>Unsupported subclass value.</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Supported subclass value.</Description>
						<Value>0</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>1</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>ERR_Kunsupp</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>ERR_KUNSUPP</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Unsupported K values</Notes>
				<Options>
					<Option>
						<Description>K value unsupported</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>K value supported</Description>
						<Value>0</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>2</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>ERR_JESDbad</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>ERR_JESDBAD</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Unsupported M/L/S/F selection</Notes>
				<Options>
					<Option>
						<Description>This JESD combination is not supported</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>This JESD combination is supported</Description>
						<Value>0</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>3</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>ERR_WinLimit</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>ERR_WINLIMIT</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Unsupported window limit</Notes>
				<Options>
					<Option>
						<Description>Unsupported SYSREF window limit.</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Supported WinLimt limit</Description>
						<Value>0</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>4</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>ERR_DlyOver</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>ERR_DLYOVER</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>LMFC_Delay &gt; JESD_K parameter</Notes>
				<Options>
					<Option>
						<Description>LMFC_Delay &gt; JESD_K</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>LMFC_Delay &lt; JESD_K</Description>
						<Value>0</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>5</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>SYNC_ERRWINDOW</Name>
		<Address>0x34</Address>
		<Description>SYNC_ERRWINDOW</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>ErrWindow</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>ERRWINDOW</Description>
				<Visibility>Public</Visibility>
				<Width>3</Width>
				<Notes>Sync error window.Synchronization rotates the clock based on a difference in the sample of the current phase of the internal clocks and the programmed target based off the SYSREF sample time. If SYSREF cannot be guaranteed to always exist in the same period of the device clock associated with the target phase from SYSREF to SYSREF (ERRWINDOW = 0), then the user may choose to apply an error window to synchronization. The error window allows the SYSREF sample phase to vary within the confines of the window without triggering a clock adjustment.</Notes>
				<Options>
					<Option>
						<Description>Error Window Tolerance +/- 0</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Error Window Tolerance +/- 1</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Error Window Tolerance +/- 2</Description>
						<Value>2</Value>
					</Option>
					<Option>
						<Description>Error Window Tolerance +/- 3</Description>
						<Value>3</Value>
					</Option>
					<Option>
						<Description>Error Window Tolerance +/- 4</Description>
						<Value>4</Value>
					</Option>
					<Option>
						<Description>Error Window Tolerance +/- 5</Description>
						<Value>5</Value>
					</Option>
					<Option>
						<Description>Error Window Tolerance +/- 6</Description>
						<Value>6</Value>
					</Option>
					<Option>
						<Description>Error Window Tolerance +/- 7</Description>
						<Value>7</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>3</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>SYNC_LASTERR_L</Name>
		<Address>0x38</Address>
		<Description>SYNC_LASTERR_L</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>LASTerror</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>LASTERROR</Description>
				<Visibility>Public</Visibility>
				<Width>4</Width>
				<Notes>Sync Last Error.LMFC Sync Last Alignment Error. 4-bit twos complement value that represents the phase error (in number of DAC clock cycles) when the clocks were last adjusted.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>4</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>SYNC_LASTERR_H</Name>
		<Address>0x39</Address>
		<Description>SYNC_LASTERR_H</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>LASTover</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>LASTOVER</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Sync last error over flag.This bit shows that the phase error between SYSREF sample point and target was above the error window limit.</Notes>
				<Options>
					<Option>
						<Description>Last phase error under window tolerance.</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Last phase error under window tolerance.</Description>
						<Value>0</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>6</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>LASTunder</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>LASTUNDER</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Sync last error under flag.This bit shows that the phase error between SYSREF sample point and target was below the error window limit.</Notes>
				<Options>
					<Option>
						<Description>Current phase error over window tolerance.</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Current phase error over window tolerance.</Description>
						<Value>0</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>7</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>SYNC_CONTROL</Name>
		<Address>0x3A</Address>
		<Description>SYNC_CONTROL</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>SyncMode</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>SYNCMODE</Description>
				<Visibility>Public</Visibility>
				<Width>4</Width>
				<Notes>Sync mode</Notes>
				<Options>
					<Option>
						<Description>Sync logic is off.</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Sync one shot mode.</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Sync continuous mode.</Description>
						<Value>8</Value>
					</Option>
					<Option>
						<Description>Sync pulsed one shot mode.</Description>
						<Value>65</Value>
					</Option>
					<Option>
						<Description>Sync pulsed continuous mode.</Description>
						<Value>72</Value>
					</Option>
					<Option>
						<Description>Sync monitor only mode.</Description>
						<Value>512</Value>
					</Option>
					<Option>
						<Description>Sync continuous, then monitor.</Description>
						<Value>520</Value>
					</Option>
					<Option>
						<Description>Sync one-shot, then monitor.</Description>
						<Value>513</Value>
					</Option>
					<Option>
						<Description>Pulsed one-shot, then monitor.</Description>
						<Value>577</Value>
					</Option>
					<Option>
						<Description>Pulsed continuous, then monitor.</Description>
						<Value>584</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>4</SliceWidth>
			</BitField>
			<BitField>
				<Name>SyncClrLAST</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>SYNCCLRLAST</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Sync clear last error</Notes>
				<Options>
					<Option>
						<Description>Clear the last errors.</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Reset clear bit.</Description>
						<Value>0</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>4</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>SyncClrStky</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>SYNCCLRSTKY</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Sync sticky bit clear</Notes>
				<Options>
					<Option>
						<Description>Clear sticky status bits REFRota and REFTrip.</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Reset clear bit.</Description>
						<Value>0</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>5</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>SyncArm</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>SYNCARM</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Sync arming strobe</Notes>
				<Options>
					<Option>
						<Description>Sync one-shot armed.</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Sync one-shot not armed.</Description>
						<Value>0</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>6</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>SyncEnable</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>SYNCENABLE</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Sync logic enable</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>7</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>SYNC_STATUS</Name>
		<Address>0x3B</Address>
		<Description>SYNC_STATUS</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>REFtrip</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>SYNC_TRIP</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Sync tripped after arming</Notes>
				<Options>
					<Option>
						<Description>Sync received SysRef pulse (sticky).</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>SysRef not yet received after clear.</Description>
						<Value>0</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>REFwlim</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>SYNC_WLIM</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Sync alignment limit range</Notes>
				<Options>
					<Option>
						<Description>Phase error outside window threshold.</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Phase error inside window threshold.</Description>
						<Value>0</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>1</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>REFrota</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>SYNC_ROTATE</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Sync rotated</Notes>
				<Options>
					<Option>
						<Description>Sync logic rotated with SysRef (sticky).</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Not yet rotated after clear.</Description>
						<Value>0</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>2</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>REFlock</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>SYNC_LOCK</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Sync alignment locked</Notes>
				<Options>
					<Option>
						<Description>Sync logic aligned within window.</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Sync locgic not aligned within window.</Description>
						<Value>0</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>3</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>REFbusy</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>SYNC_BUSY</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Sync machine busy</Notes>
				<Options>
					<Option>
						<Description>Sync logic SM is busy.</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Sync logic SM not busy.</Description>
						<Value>0</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>7</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>SYNC_CURRERR_L</Name>
		<Address>0x3C</Address>
		<Description>SYNC_CURRERR_L</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>CURRerror</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>CURRERROR</Description>
				<Visibility>Public</Visibility>
				<Width>4</Width>
				<Notes>Sync alignment error.LMFC Sync Alignment Error. 4-bit twos complement value that represents the phase error in number of DAC clock cycles (ie, number of DAC clocks between LMFC edge and SYSREF edge).
When an adjustment of the clocks is made on any given SYSREF, the value of the phase error is placed into SYNC_LASTERR, and SYNC_CURRERR is forced to 0.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>4</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>SYNC_CURRERR_H</Name>
		<Address>0x3D</Address>
		<Description>SYNC_CURRERR_H</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>CURRover</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>CURROVER</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Sync current error over flag</Notes>
				<Options>
					<Option>
						<Description>Current phase error over window tolerance.</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Current phase error not over window tolerance.</Description>
						<Value>0</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>6</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>CURRunder</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>CURRUNDER</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Sync current error under flag</Notes>
				<Options>
					<Option>
						<Description>Current phase error under window tolerance.</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Current phase error not under window tolerance.</Description>
						<Value>0</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>7</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>DACGAIN0_1</Name>
		<Address>0x40</Address>
		<Description>DACGAIN0_1</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>dacgain_il0[9:8]</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>DACGAIN_IL0[9:8]</Description>
				<Visibility>Public</Visibility>
				<Width>2</Width>
				<Notes>I Channel DAC gain Dual A.DACGAIN0_0 and DACGAIN0_1 together are the analog full-scale current control for DAC0 (I-Channel Dual A). Two's complement encoding is as follows:
01111111111 = 26.4mA
0000000000 = 20mA
1000000000 = 13.6mA</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>2</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>DACGAIN0_0</Name>
		<Address>0x41</Address>
		<Description>DACGAIN0_0</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>dacgain_il0[7:0]</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>DACGAIN_IL0[7:0]</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>I Channel DAC gain Dual A.DACGAIN0_0 and DACGAIN0_1 together are the analog full-scale current control for DAC0 (I-Channel Dual A). Two's complement encoding is as follows:
01111111111 = 26.4mA
0000000000 = 20mA
1000000000 = 13.6mA</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>DACGAIN1_1</Name>
		<Address>0x42</Address>
		<Description>DACGAIN1_1</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>dacgain_il1[9:8]</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>DACGAIN_IL1[9:8]</Description>
				<Visibility>Public</Visibility>
				<Width>2</Width>
				<Notes>Q Channel DAC gain Dual A.DACGAIN1_0 and DACGAIN1_1 together are the analog full-scale current control for DAC1 (Q-Channel Dual A). Two's complement encoding is as follows:
01111111111 = 26.4mA
0000000000 = 20mA
1000000000 = 13.6mA</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>2</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>DACGAIN1_0</Name>
		<Address>0x43</Address>
		<Description>DACGAIN1_0</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>dacgain_il1[7:0]</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>DACGAIN_IL1[7:0]</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Q Channel DAC gain Dual A.DACGAIN1_0 and DACGAIN1_1 together are the analog full-scale current control for DAC1 (Q-Channel Dual A). Two's complement encoding is as follows:
01111111111 = 26.4mA
0000000000 = 20mA
1000000000 = 13.6mA</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>DACGAIN2_1</Name>
		<Address>0x44</Address>
		<Description>DACGAIN2_1</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>dacgain_il2[9:8]</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>DACGAIN_IL2[9:8]</Description>
				<Visibility>Public</Visibility>
				<Width>2</Width>
				<Notes>I Channel DAC gain Dual B.DACGAIN2_0 and DACGAIN2_1 together are the analog full-scale current control for DAC2 (I-Channel Dual B). Two's complement encoding is as follows:
01111111111 = 26.4mA
0000000000 = 20mA
1000000000 = 13.6mA</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>2</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>DACGAIN2_0</Name>
		<Address>0x45</Address>
		<Description>DACGAIN2_0</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>dacgain_il2[7:0]</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>DACGAIN_IL2[7:0]</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>I Channel DAC gain Dual B.DACGAIN2_0 and DACGAIN2_1 together are the analog full-scale current control for DAC2 (I-Channel Dual B). Two's complement encoding is as follows:
01111111111 = 26.4mA
0000000000 = 20mA
1000000000 = 13.6mA</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>DACGAIN3_1</Name>
		<Address>0x46</Address>
		<Description>DACGAIN3_1</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>dacgain_il3[9:8]</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>DACGAIN_IL3[9:8]</Description>
				<Visibility>Public</Visibility>
				<Width>2</Width>
				<Notes>Q Channel DAC gain Dual B.DACGAIN3_0 and DACGAIN3_1 together are the analog full-scale current control for DAC3 (Q-Channel Dual B). Two's complement encoding is as follows:
01111111111 = 26.4mA
0000000000 = 20mA
1000000000 = 13.6mA</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>2</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>DACGAIN3_0</Name>
		<Address>0x47</Address>
		<Description>DACGAIN3_0</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>dacgain_il3[7:0]</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>DACGAIN_IL3[7:0]</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Q Channel DAC gain Dual B.DACGAIN3_0 and DACGAIN3_1 together are the analog full-scale current control for DAC3 (Q-Channel Dual B). Two's complement encoding is as follows:
01111111111 = 26.4mA
0000000000 = 20mA
1000000000 = 13.6mA</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>NCOALIGN_MODE</Name>
		<Address>0x50</Address>
		<Description>NCOALIGN_MODE</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>NcoClrMode</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>NCO_ALIGN_MODE</Description>
				<Visibility>Public</Visibility>
				<Width>2</Width>
				<Notes>NCO clear mode</Notes>
				<Options>
					<Option>
						<Description>NCO align disabled</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>NCO align on data key.</Description>
						<Value>8</Value>
					</Option>
					<Option>
						<Description>NCO align on SYSREF</Description>
						<Value>1</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>2</SliceWidth>
			</BitField>
			<BitField>
				<Name>NcoClrFAIL</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>NCO_ALIGN_FAIL</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>NCO clear fail</Notes>
				<Options>
					<Option>
						<Description>NCO reset during rotate.</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Not finished yet.</Description>
						<Value>0</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>3</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>NcoClrPASS</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>NCO_ALIGN_PASS</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>NCO clear pass</Notes>
				<Options>
					<Option>
						<Description>NCO clear takes effect.</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Clear not taken effect yet.</Description>
						<Value>0</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>4</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>NcoClrMTCH</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>NCO_ALIGN_MTCH</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>NCO clear data match</Notes>
				<Options>
					<Option>
						<Description>Key NCO clear data match.</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>If finished, NCO not cleared on data match.</Description>
						<Value>0</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>5</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>NcoClrArm</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>NCO_ALIGN_ARM</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Arm NCO clear.Arms NCO clearing operation.</Notes>
				<Options>
					<Option>
						<Description>Arm NCO clear logic</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Not arming NCO clear logic</Description>
						<Value>0</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>7</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>NCOKEY_ILSB</Name>
		<Address>0x51</Address>
		<Description>NCOKEY_ILSB</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>NcoKeyI[7:0]</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>NCOKEYI[7:0]</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>NCO DataKey for I Channel</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>NCOKEY_IMSB</Name>
		<Address>0x52</Address>
		<Description>NCOKEY_IMSB</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>NcoKeyI[15:8]</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>NCOKEYI[15:8]</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>NCO DataKey for I Channel</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>NCOKEY_QLSB</Name>
		<Address>0x53</Address>
		<Description>NCOKEY_QLSB</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>NcoKeyQ[7:0]</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>NCOKEYQ[7:0]</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>NCO DataKey for Q Channel</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>NCOKEY_QMSB</Name>
		<Address>0x54</Address>
		<Description>NCOKEY_QMSB</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>NcoKeyQ[15:8]</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>NCOKEYQ[15:8]</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>NCO DataKey for Q Channel</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>PDP_THRES0</Name>
		<Address>0x60</Address>
		<Description>PDP_THRES0</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>pa_threshold[7:0]</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>PA_THRESHOLD[7:0]</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Average power threshold for comparison</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>PDP_THRES1</Name>
		<Address>0x61</Address>
		<Description>PDP_THRES1</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>pa_threshold[12:8]</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>PA_THRESHOLD[12:8]</Description>
				<Visibility>Public</Visibility>
				<Width>5</Width>
				<Notes>Average power threshold for comparison</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>5</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>PDP_AVG_TIME</Name>
		<Address>0x62</Address>
		<Description>PDP_AVG_TIME</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>pa_avg_time</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>PDP_AVG_TIME</Description>
				<Visibility>Public</Visibility>
				<Width>4</Width>
				<Notes>Set power average time</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>4</SliceWidth>
			</BitField>
			<BitField>
				<Name>pa_enable</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>PDP_ENABLE</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Set this bit high to enable average power calculation and error detection</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>7</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>PDP_POWER0</Name>
		<Address>0x63</Address>
		<Description>PDP_POWER0</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>pa_power[7:0]</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>PA_POWER[7:0]</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Average power bus =\sup{I}{2}+\sup{Q}{2} (I/Q use 6 MSB of databus)</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>PDP_POWER1</Name>
		<Address>0x64</Address>
		<Description>PDP_POWER1</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>pa_power[12:8]</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>PA_POWER[12:8]</Description>
				<Visibility>Public</Visibility>
				<Width>5</Width>
				<Notes>Average power bus =\sup{I}{2}+\sup{Q}{2} (I/Q use 6 MSB of databus)</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>5</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>CLKCFG0</Name>
		<Address>0x80</Address>
		<Description>CLKCFG0</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>pd_clk_rec</Name>
				<Access>R/W</Access>
				<DefaultValue>1</DefaultValue>
				<Description>PD_CLK_REC</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Clock reciever powerdown.This bit powers down the analog DAC clock receiver block. With this bit set, clocks will not  make their way to the device internal nets.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>3</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>pd_pclk</Name>
				<Access>R/W</Access>
				<DefaultValue>1</DefaultValue>
				<Description>POWER DOWN SERDES PCLK</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Cal reference/Serdes PLL clock powerdown.This bits disables the PCLK inside the part. The PCLK is used for 4 functions:
1. Provide a clock to the powerdown machines for the DAC.
2. Provide a clock to the AUX ADC for conversion.
3. Provide a baseline clock for the DAC calibration.
   The three clocks above must further be enabled in Register 0x1C6[1].
4. Provide a reference clock to the Serdes PLL in order to have operational serial interface.
   This final clock is active regardless of Register 0x1C6[1].</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>4</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>pd_clk_dig</Name>
				<Access>R/W</Access>
				<DefaultValue>1</DefaultValue>
				<Description>PD_CLK_DIG</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Powerdown clocks to all DACs.The bit disables all the clock path from the DAC clock receiver to the digital. This includes all reference clocks, PCLK, DAC clocks, and digital clocks.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>5</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>pd_clk23</Name>
				<Access>R/W</Access>
				<DefaultValue>1</DefaultValue>
				<Description>PD_CLK23</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Powerdown clock for Dual B.The bit disables the digital clocks for the Dual DAC and Dual digital for Dual B.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>6</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>pd_clk01</Name>
				<Access>R/W</Access>
				<DefaultValue>1</DefaultValue>
				<Description>PD_CLK01</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Powerdown clock for Dual A.The bit disables the digital clocks for the DACs and digital blocks for Dual A.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>7</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>SYSREF_ACTRL0</Name>
		<Address>0x81</Address>
		<Description>SYSREF_ACTRL0</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>hys_cntrl1</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>HYS_CNTRL1</Description>
				<Visibility>Public</Visibility>
				<Width>2</Width>
				<Notes>Hysteresis control bits &lt;9:8&gt;.Hysteresis control bits are control bits for the amount of hysteresis in the SYSREF receiver. Each of the ten bits adds 10mV of differential hysteresis to the receiver input. The two MSB bits are contained here. The 8 LSB bits are in hys_cntrl0.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>2</SliceWidth>
			</BitField>
			<BitField>
				<Name>sysref_rise</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>SYSREF_RISE</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Use SYSREF rising edge</Notes>
				<Options>
					<Option>
						<Description>Use SYSREF falling edge for alignment</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Use SYSREF rising edge for alignment</Description>
						<Value>1</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>2</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>hys_on</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>HYS_ON</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Hysteresis enabled.This bit enables the programmable hysteresis control for the SYSREF receiver.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>3</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>pd_sysref</Name>
				<Access>R/W</Access>
				<DefaultValue>1</DefaultValue>
				<Description>POWER DOWN SYSREF BUFFER</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Powerdown SYSREF buffer.This bit powers down the SYSREF receiver. For subclass 1 operation to work, this buffer must be enabled.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>4</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>SYSREF_ACTRL1</Name>
		<Address>0x82</Address>
		<Description>SYSREF_ACTRL1</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>hys_cntrl0</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>HYS_CNTRL0</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Hysteresis control &lt;7:0&gt;.Hysteresis control bits are control bits for the amount of hysteresis in the SYSREF receiver. Each of the ten bits adds 10mV of differential hysteresis to the receiver input. The 8 LSB bits are contained here. The 2 MSB bits are in hys_cntrl1.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>DACPLLCNTRL</Name>
		<Address>0x83</Address>
		<Description>DACPLLCNTRL</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>enable_synth</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>ENABLE_DACPLL</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Synthesizer Enable.The bit initiates the startup sequence of the DAC PLL. The startup sequence is as follows:
1. Enable the bias currents
2. Enable DAC LDO
3. Wait for LDO to settle
4. Calibrate DAC PLL charge pump (The DAC charge pump will only calibrate upon the first setting of enable_synth)
5. Calibrate the band of the PLL
6. Settle and lock.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>4</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>synth_recal</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>RECAL_DACPLL</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Recalibrate VCO Band.Set this bit to re-initialize the calibration of the VCO band in the DAC PLL. This bit will not power cycle the DAC PLL, nor will it recalibrate the charge pump. This bit should be set after changing any setting associated with the PLL. It should be set until an initial PLL lock is achieved.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>7</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>DACPLLSTATUS</Name>
		<Address>0x84</Address>
		<Description>DACPLLSTATUS</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>rfpll_lock</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>DACPLL_LOCK</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>PLL Lock bit.This bit will be set high by the PLL once the PLL has achieved lock for the count set by lock_mode bits in register 0x1C0.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>1</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>cp_cal_valid</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>DACPLL_CAL_VALID</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Charge Pump Cal Valid.This bit indicates that the charge pump has been successfully calibrated. Register 0x1B9 contains the selection for whether or not to calibrate the charge pump.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>5</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>cp_overrange_l</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>DACPLL_OVERRANGE_L</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Charge Pump Low Overrange.This bit indicates that the charge pump voltage is too low and a recalibration should be applied.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>6</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>cp_overrange_h</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>DACPLL_OVERRANGE_H</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Charge Pump High Overrange.This bit indicates that the charge pump voltage is too high and a recalibration should be applied.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>7</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>DACIntegerWord0</Name>
		<Address>0x85</Address>
		<Description>DACINTEGERWORD0</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>freq_int1</Name>
				<Access>R/W</Access>
				<DefaultValue>8</DefaultValue>
				<Description>B_COUNT</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Integer division word.This bit controls the integer feedback divider for the DAC PLL. The frequency of the DAC clock can be determined by the following:
F(dac) = Fref/(ref_divrate) * 2 * freq_int1
F(vco) = Fref/(ref_divrate) * 2 * freq_int1 * lo_div_mode
Minimum value is 6.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>DACLoopFilt1</Name>
		<Address>0x87</Address>
		<Description>DACLOOPFILT1</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>lf_c1_word</Name>
				<Access>R/W</Access>
				<DefaultValue>8</DefaultValue>
				<Description>LF_C1_WORD</Description>
				<Visibility>Public</Visibility>
				<Width>4</Width>
				<Notes>C1 control word.See Lookup Tables for values associated with C1</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>4</SliceWidth>
			</BitField>
			<BitField>
				<Name>lf_c2_word</Name>
				<Access>R/W</Access>
				<DefaultValue>8</DefaultValue>
				<Description>LF_C2_WORD</Description>
				<Visibility>Public</Visibility>
				<Width>4</Width>
				<Notes>C2 control word.See Lookup Tables for values associated with C2</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>4</RegOffset>
				<SliceWidth>4</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>DACLoopFilt2</Name>
		<Address>0x88</Address>
		<Description>DACLOOPFILT2</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>lf_c3_word</Name>
				<Access>R/W</Access>
				<DefaultValue>8</DefaultValue>
				<Description>LF_C3_WORD</Description>
				<Visibility>Public</Visibility>
				<Width>4</Width>
				<Notes>C3 control word.See Lookup Tables for values associated with C3</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>4</SliceWidth>
			</BitField>
			<BitField>
				<Name>lf_r1_word</Name>
				<Access>R/W</Access>
				<DefaultValue>8</DefaultValue>
				<Description>LF_R1_WORD</Description>
				<Visibility>Public</Visibility>
				<Width>4</Width>
				<Notes>R1 control word.See Lookup Tables for values associated with R1</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>4</RegOffset>
				<SliceWidth>4</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>DACLoopFilt3</Name>
		<Address>0x89</Address>
		<Description>DACLOOPFILT3</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>lf_r3_word</Name>
				<Access>R/W</Access>
				<DefaultValue>8</DefaultValue>
				<Description>LF_R3_WORD</Description>
				<Visibility>Public</Visibility>
				<Width>4</Width>
				<Notes>R3 Control Word.See Lookup Tables for values associated with R3</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>4</SliceWidth>
			</BitField>
			<BitField>
				<Name>lf_bypass_c1</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>LF_BYPASS_C1</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Bypass C1 capacitor.If this bit is set, Bypass C1 capacitor (set to 0pF) if C1_word is set to 0.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>4</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>lf_bypass_c2</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>LF_BYPASS_C2</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Bypass C2 capacitor.If this bit is set, Bypass C2 capacitor (set to 0pF) if C2_word is set to 0.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>5</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>lf_bypass_r1</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>LF_BYPASS_R1</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Bypass R1 resistor.If this bit is set, Bypass r1 capacitor (set to 0pF) if r1_word is set to 0.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>6</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>lf_bypass_r3</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>LF_BYPASS_R3</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Bypass R3 resistor.If this bit is set, Bypass r3 capacitor (set to 0pF) if r3_word is set to 0.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>7</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>DACCPcntrl</Name>
		<Address>0x8A</Address>
		<Description>DACCPCNTRL</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>cp_current</Name>
				<Access>R/W</Access>
				<DefaultValue>32</DefaultValue>
				<Description>CP_CURRENT</Description>
				<Visibility>Public</Visibility>
				<Width>6</Width>
				<Notes>Charge Pump Current Control.See Lookup Tables for values associated with Charge Pump Current.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>6</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>DACLogencntrl</Name>
		<Address>0x8B</Address>
		<Description>DACLOGENCNTRL</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>lo_div_mode</Name>
				<Access>R/W</Access>
				<DefaultValue>2</DefaultValue>
				<Description>LO_DIV_MODE</Description>
				<Visibility>Public</Visibility>
				<Width>2</Width>
				<Notes>Logen_Division.This range controls the RF clock divider between the VCO and DAC clock rate. The options are 4x, 8x, or 16x division. The F(vco) can be found by:
F(vco) = Fref/(ref_divrate) * 2 * freq_int1 * lo_div_mode</Notes>
				<Options>
					<Option>
						<Description>Divide by 4 - VCO to DAC clock</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Divide by 8 - VCO to DAC clock</Description>
						<Value>8</Value>
					</Option>
					<Option>
						<Description>Divide by 16 - VCO to DAC clock</Description>
						<Value>9</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>2</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>DACLDOcntrl1</Name>
		<Address>0x8C</Address>
		<Description>DACLDOCNTRL1</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>ref_divrate</Name>
				<Access>R/W</Access>
				<DefaultValue>1</DefaultValue>
				<Description>REF_DIV_MODE</Description>
				<Visibility>Public</Visibility>
				<Width>3</Width>
				<Notes>Reference Clock Division Ratio.This field controls the amount of division that is done to the input clock at the CLK+/CLK- pins before it is presented to the PLL as a reference clock. The Reference clock frequency must be between 35-80 MHz, but the CLK in frequency can range from 35 MHz to 1 GHz. The user shall set this division in order to achieve 35-80 MHz PLL reference frequency.</Notes>
				<Options>
					<Option>
						<Description>1x</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>2x</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>4x</Description>
						<Value>8</Value>
					</Option>
					<Option>
						<Description>8x</Description>
						<Value>9</Value>
					</Option>
					<Option>
						<Description>16x</Description>
						<Value>64</Value>
					</Option>
					<Option>
						<Description>32x</Description>
						<Value>65</Value>
					</Option>
					<Option>
						<Description>16x</Description>
						<Value>72</Value>
					</Option>
					<Option>
						<Description>32x</Description>
						<Value>73</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>3</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>CAL_CTRL_GLOBAL</Name>
		<Address>0xE2</Address>
		<Description>CAL_CTRL_GLOBAL</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>CAL_EN_GL</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>CAL_EN_AVG</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Global Calibration enable.Enable the calibration DACs of all DACs. Enable to calibration engine and machines. Prepare for a Calibration start. In order for Calibration coefficients to be applied to the Calibrated DACs, this bit must be high.</Notes>
				<Options>
					<Option>
						<Description>Disable Global CAL DAC machine</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Enable Global CAL DAC machine</Description>
						<Value>1</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>CAL_START_GL</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>CAL_START_AVG</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Global Calibration start.The rising edge of this bit kicks off a calibration sequence for the DACs which have been selected in the CAL_INDX register.</Notes>
				<Options>
					<Option>
						<Description>Normal operation</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Start calibration state machine</Description>
						<Value>1</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>1</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>CAL_CLKDIV</Name>
		<Address>0xE7</Address>
		<Description>CAL_CLKDIV</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>CAL_CLKDIV</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>CAL_CLK_EN</Description>
				<Visibility>Public</Visibility>
				<Width>4</Width>
				<Notes>Calibration clock divider.This field controls the division factor from the PCLK to the DAC CAL clock. The PCLK frequency is set by: 
F(pclk) = (DACCLK/Interpolation * 4/(F*S))</Notes>
				<Options>
					<Option>
						<Description>Disable calibration clock</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>divide by \sup{2}{20}</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>divide by \sup{2}{19}</Description>
						<Value>8</Value>
					</Option>
					<Option>
						<Description>divide by \sup{2}{18}</Description>
						<Value>9</Value>
					</Option>
					<Option>
						<Description>divide by \sup{2}{17}</Description>
						<Value>64</Value>
					</Option>
					<Option>
						<Description>divide by \sup{2}{16}</Description>
						<Value>65</Value>
					</Option>
					<Option>
						<Description>divide by \sup{2}{15}</Description>
						<Value>72</Value>
					</Option>
					<Option>
						<Description>divide by \sup{2}{14}</Description>
						<Value>73</Value>
					</Option>
					<Option>
						<Description>divide by \sup{2}{13}</Description>
						<Value>512</Value>
					</Option>
					<Option>
						<Description>divide by \sup{2}{12}</Description>
						<Value>513</Value>
					</Option>
					<Option>
						<Description>divide by \sup{2}{11}</Description>
						<Value>520</Value>
					</Option>
					<Option>
						<Description>divide by \sup{2}{10}</Description>
						<Value>521</Value>
					</Option>
					<Option>
						<Description>divide by \sup{2}{9}</Description>
						<Value>576</Value>
					</Option>
					<Option>
						<Description>divide by 2^9</Description>
						<Value>577</Value>
					</Option>
					<Option>
						<Description>divide by 2^9</Description>
						<Value>584</Value>
					</Option>
					<Option>
						<Description>divide by 2^9</Description>
						<Value>585</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>4</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>CAL_PAGE</Name>
		<Address>0xE8</Address>
		<Description>CAL_PAGE</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>CAL_INDX</Name>
				<Access>R/W</Access>
				<DefaultValue>15</DefaultValue>
				<Description>CAL_PAGE</Description>
				<Visibility>Public</Visibility>
				<Width>4</Width>
				<Notes>DAC Calibration Index paging bits.DAC Calibration Index.  These are paging bits which select which of the DACs are being accessed for calibration or calibration readback.
Write/Calibration: All DACs can be accessed at once to write CAL DAC information or to calibrate.
Readback: Only one DAC at a time can be accessed when reading back CAL DAC information.</Notes>
				<Options>
					<Option>
						<Description>None</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>DAC0 accessed</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>DAC1 accessed</Description>
						<Value>2</Value>
					</Option>
					<Option>
						<Description>DAC2 accessed</Description>
						<Value>4</Value>
					</Option>
					<Option>
						<Description>DAC3 accessed</Description>
						<Value>8</Value>
					</Option>
					<Option>
						<Description>All accessed</Description>
						<Value>15</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>4</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>CAL_CTRL</Name>
		<Address>0xE9</Address>
		<Description>CAL_CTRL</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>CAL_EN</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>CAL_EN</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Calibration enable.Enable the calibration DAC of the converter. Enable to calibration engine and machines. Prepare for a calibration start. In order for calibration coefficients to be applied to the Calibrated DACs, this bit must be high.</Notes>
				<Options>
					<Option>
						<Description>Do not use CAL DAC's</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Use CAL DAC's</Description>
						<Value>1</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>CAL_START</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>CAL_START</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Calibration start.The rising edge of this bit kicks off a calibration sequence for the DACs which have been selected in the CAL_INDX register.</Notes>
				<Options>
					<Option>
						<Description>Normal operation</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Start calibration state machine</Description>
						<Value>1</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>1</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>CAL_ERRLO</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>CAL_ERRLO</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>SAR data error: too low.This bit will be set at the end of a cal cycle if any of the CAL DACs has over-ranged to the low side. This typically means that the algorithm will adjust the cal preset of the CAL DACs and run another cycle.</Notes>
				<Options>
					<Option>
						<Description>Data in range</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Data saturated low</Description>
						<Value>1</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>4</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>CAL_ERRHI</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>CAL_ERRHI</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>SAR data error: too high.This bit will be set at the end of a cal cycle if any of the CAL DACs has over-ranged to the high side. This typically means that the algorithm will adjust the cal preset of the CAL DACs and run another cycle.</Notes>
				<Options>
					<Option>
						<Description>Data in range</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Data saturated high</Description>
						<Value>1</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>5</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>CAL_ACTIVE</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>CAL_ACTIVE</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Calibration active.This bit will be high while CAL is in progress.</Notes>
				<Options>
					<Option>
						<Description>Calibration is running</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Calibration is not running</Description>
						<Value>1</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>6</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>CAL_FIN</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>CAL_FIN</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Calibration finished.This bit will be high if the calibration has completed. If the calibration completes and either CAL_ERRHI or CAL_ERRLO is high then the calibration can not be considered valid and should be considered a timeout event.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>7</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>CAL_INIT</Name>
		<Address>0xED</Address>
		<Description>CAL_INIT</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>CAL_INIT</Name>
				<Access>R/W</Access>
				<DefaultValue>38</DefaultValue>
				<Description>CAL_INIT</Description>
				<Visibility>Public</Visibility>
				<Width>6</Width>
				<Notes>Calibration DAC ISBREF initial value.This value is a starting set point for the ISB CAL DACs chosen to make sure that the SAR algorithms will not overflow in the first cycle.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>6</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>DATA_FORMAT</Name>
		<Address>0x110</Address>
		<Description>DATA_FORMAT</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>binary_format</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>BINARY_FORMAT</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Binary or twos complementary format on data bus</Notes>
				<Options>
					<Option>
						<Description>Input data is twos complement</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Input data is offset binary</Description>
						<Value>1</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>7</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>DATAPATH_CTRL</Name>
		<Address>0x111</Address>
		<Description>DATAPATH_CTRL</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>i_to_q</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>I_TO_Q</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Send I data into Q DAC .This is different than sel_sideband bit which allow for I/Q swapping in front of datapath and positive/negative frequency shift.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>sel_sideband</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>SEL_SIDEBAND</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Spectrum inversion control.When this bit is high, the I and Q datapaths are swapped before entering the modulator, causing the spectrum to invert.
ie. 
If set to 0:
I DAC = I X cos - Q X sin
Q DAC = I X sin + Q X cos
If set to 1:
I DAC = Q X cos - I X sin
Q DAC = Q X sin + I X cos</Notes>
				<Options>
					<Option>
						<Description>I and Q data are not swapped before entering the modulator.</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>I and Q are swapped before entering the modulator.</Description>
						<Value>1</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>1</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>modulation_type</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>MODULATION_TYPE</Description>
				<Visibility>Public</Visibility>
				<Width>2</Width>
				<Notes>Selects type of modulation operation</Notes>
				<Options>
					<Option>
						<Description>No modulation</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Fine modulation (uses FTW)</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>fs/4 modulation</Description>
						<Value>8</Value>
					</Option>
					<Option>
						<Description>fs/8 modulation</Description>
						<Value>9</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>2</RegOffset>
				<SliceWidth>2</SliceWidth>
			</BitField>
			<BitField>
				<Name>phase_adj_enable</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>PHASE_ADJ_ENABLE</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Enable phase compensation</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>4</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>dig_gain_enable</Name>
				<Access>R/W</Access>
				<DefaultValue>1</DefaultValue>
				<Description>DIG_GAIN_ENABLE</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Enable digital gain</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>5</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>invsinc_enable</Name>
				<Access>R/W</Access>
				<DefaultValue>1</DefaultValue>
				<Description>INVSINC_ENABLE</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Enable inverse sinc filter</Notes>
				<Options>
					<Option>
						<Description>Enable inverse sinc filter.</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Disable inverse sinc filter.</Description>
						<Value>0</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>7</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>INTERP_MODE</Name>
		<Address>0x112</Address>
		<Description>INTERP_MODE</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>INTERP_MODE</Name>
				<Access>R/W</Access>
				<DefaultValue>1</DefaultValue>
				<Description>INTERP_MODE</Description>
				<Visibility>Public</Visibility>
				<Width>3</Width>
				<Notes>Interpolation Mode</Notes>
				<Options>
					<Option>
						<Description>1x mode (bypass)</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>2x mode</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>4x mode</Description>
						<Value>9</Value>
					</Option>
					<Option>
						<Description>8x mode</Description>
						<Value>64</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>3</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>NCO_FTW_UPDATE</Name>
		<Address>0x113</Address>
		<Description>NCO_FTW_UPDATE</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>ftw_update_req</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>FTW_UPDATE_REQ</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Frequency tuning word update request from SPI</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>ftw_update_ack</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>FTW_UPDATE_ACK</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Frequency tuning word update acknowledge</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>1</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>FTW0</Name>
		<Address>0x114</Address>
		<Description>FTW0</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>FTW[7:0]</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>FTW[7:0]</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>NCO frequency tuning word</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>FTW1</Name>
		<Address>0x115</Address>
		<Description>FTW1</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>FTW[15:8]</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>FTW[15:8]</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>NCO frequency tuning word</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>FTW2</Name>
		<Address>0x116</Address>
		<Description>FTW2</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>FTW[23:16]</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>FTW[23:16]</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>NCO frequency tuning word</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>FTW3</Name>
		<Address>0x117</Address>
		<Description>FTW3</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>FTW[31:24]</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>FTW[31:24]</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>NCO frequency tuning word</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>FTW4</Name>
		<Address>0x118</Address>
		<Description>FTW4</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>FTW[39:32]</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>FTW[39:32]</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>NCO frequency tuning word</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>FTW5</Name>
		<Address>0x119</Address>
		<Description>FTW5</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>FTW[47:40]</Name>
				<Access>R/W</Access>
				<DefaultValue>16</DefaultValue>
				<Description>FTW[47:40]</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>NCO frequency tuning word</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>NCO_PHASE_OFFSET0</Name>
		<Address>0x11A</Address>
		<Description>NCO_PHASE_OFFSET0</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>nco_phase_offset[7:0]</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>NCO_PHASE_OFFSET[7:0]</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>NCO phase offset</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>NCO_PHASE_OFFSET1</Name>
		<Address>0x11B</Address>
		<Description>NCO_PHASE_OFFSET1</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>nco_phase_offset[15:8]</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>NCO_PHASE_OFFSET[15:8]</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>NCO phase offset</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>PHASE_ADJ0</Name>
		<Address>0x11C</Address>
		<Description>PHASE_ADJ0</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>phase_adj[7:0]</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>PHASE_ADJ[7:0]</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Phase compensation word.Phase compensation control is a 13-bit signed twos complement value.  The control ranges from -14 degrees to +14 degrees with 0.0035 degree resolution steps.  Register 0x11C bits [7:0] are the LSB and Register 0x11D bits [12:8] are the MSB.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>PHASE_ADJ1</Name>
		<Address>0x11D</Address>
		<Description>PHASE_ADJ1</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>phase_adj[12:8]</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>PHASE_ADJ[12:8]</Description>
				<Visibility>Public</Visibility>
				<Width>5</Width>
				<Notes>Phase compensation word.Phase compensation control is a 13-bit signed twos complement value.  The control ranges from -14 degrees to +14 degrees with 0.0035 degree resolution steps.  Register 0x11C bits [7:0] are the LSB and Register 0x11D bits [12:8] are the MSB.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>5</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>TXEN_SM_0</Name>
		<Address>0x11F</Address>
		<Description>TXEN_SM_0</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>gp_pa_on_invert</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>PROTECT_OUT_INVERT</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>External modulator polarity invert</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>2</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>pa_rise</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>RISE_COUNTERS</Description>
				<Visibility>Public</Visibility>
				<Width>2</Width>
				<Notes>PDP rise control</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>4</RegOffset>
				<SliceWidth>2</SliceWidth>
			</BitField>
			<BitField>
				<Name>pa_fall</Name>
				<Access>R/W</Access>
				<DefaultValue>2</DefaultValue>
				<Description>FALL_COUNTERS</Description>
				<Visibility>Public</Visibility>
				<Width>2</Width>
				<Notes>PDP fall control</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>6</RegOffset>
				<SliceWidth>2</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>TXEN_RISE_COUNT_0</Name>
		<Address>0x121</Address>
		<Description>TXEN_RISE_COUNT_0</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>maxA</Name>
				<Access>R/W</Access>
				<DefaultValue>15</DefaultValue>
				<Description>RISE_COUNT_0</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Clock count threshold.This value sets the amount of clock cycles between event 1 (E1) and event 2 (E2).  Event 1 is defined as the time the TXEN pin is brought high.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>TXEN_RISE_COUNT_1</Name>
		<Address>0x122</Address>
		<Description>TXEN_RISE_COUNT_1</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>maxB</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>RISE_COUNT_1</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Clock count threshold.This value sets the amount of clock cycles between event 2 (E2) and event 3 (E3).  Event 1 is defined as the time the TXEN pin is brought high.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>TXEN_FALL_COUNT_0</Name>
		<Address>0x123</Address>
		<Description>FALL_COUNT_0</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>maxC</Name>
				<Access>R/W</Access>
				<DefaultValue>255</DefaultValue>
				<Description>FALL_COUNT_0</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Clock count threshold.This value sets the amount of clock cycles between event 4 (E4) and event 5 (E5).  Event 4 is defined as the time the TXEN pin is brought low.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>TXEN_FALL_COUNT_1</Name>
		<Address>0x124</Address>
		<Description>TXEN_FALL_COUNT_1</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>maxD</Name>
				<Access>R/W</Access>
				<DefaultValue>255</DefaultValue>
				<Description>FALL_COUNT_1</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Clock count threshold.This value sets the amount of clock cycles between event 5 (E5) and event 6 (E6).  Event 4 is defined as the time the TXEN pin is brought low.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>DEVICE_CONFIG_REG_0</Name>
		<Address>0x12D</Address>
		<Description>DEVICE_CONFIG_REG_0</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>DEVICE_CONFIG_0</Name>
				<Access>R/W</Access>
				<DefaultValue>70</DefaultValue>
				<Description>DEVICE_CONFIG_0</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Must be set to 0x8B for proper digital datapath configuration.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>DIE_TEMP_CTRL0</Name>
		<Address>0x12F</Address>
		<Description>DIE_TEMP_CTRL0</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>AUXADC_ENABLE</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>AUXADC_ENABLE</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Enables the AUX ADC block</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>DIE_TEMP0</Name>
		<Address>0x132</Address>
		<Description>DIE_TEMP0</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>DIE_TEMP[7:0]</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>DIE_TEMP[7:0]</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Aux ADC readback value</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>DIE_TEMP1</Name>
		<Address>0x133</Address>
		<Description>DIE_TEMP1</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>DIE_TEMP[15:8]</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>DIE_TEMP[15:8]</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Aux ADC readback value</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>DIE_TEMP_UPDATE</Name>
		<Address>0x134</Address>
		<Description>DIE_TEMP_UPDATE</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>DIE_TEMP_UPDATE</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>DIE_TEMP_UPDATE</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Die temperature update. When updated, new temperature code is generated</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>DC_OFFSET_CTRL</Name>
		<Address>0x135</Address>
		<Description>DC_OFFSET_CTRL</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>DC_OFFSET_ON</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>DC_OFFSET_ON</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>1 = enable dc offset module</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>IPATH_DC_OFFSET_1PART0</Name>
		<Address>0x136</Address>
		<Description>IPATH_DC_OFFSET_1PART0</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>IPATH_DC_OFFSET_1PART[7:0]</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>IPATH_DC_OFFSET_1PART[7:0]</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Part 1 of the I DAC DC offset control. This part is a 1.15 signed max number and is combined with part 2 (1.4 signed max number) to form a 1.19 signed max DC offset value.Register 0x137 (MSB) and Register 0x136 (LSB) together set the 16 bit twos complement DC offset value for the I DAC with a max value of 1.15.  The page index value in Register 0x08 dictates which Dual I DAC will be programmed.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>IPATH_DC_OFFSET_1PART1</Name>
		<Address>0x137</Address>
		<Description>IPATH_DC_OFFSET_1PART1</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>IPATH_DC_OFFSET_1PART[15:8]</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>IPATH_DC_OFFSET_1PART[15:8]</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Part 1 of the I DAC DC offset control. This part is a 1.15 signed max number and is combined with part 2 (1.4 signed max number) to form a 1.19 signed max DC offset value.Register 0x137 (MSB) and Register 0x136 (LSB) together set the 16 bit twos complement DC offset value for the I DAC with a max value of 1.15.  The page index value in Register 0x08 dictates which Dual I DAC will be programmed.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>QPATH_DC_OFFSET_1PART0</Name>
		<Address>0x138</Address>
		<Description>QPATH_DC_OFFSET_1PART0</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>QPATH_DC_OFFSET_1PART[7:0]</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>QPATH_DC_OFFSET_1PART[7:0]</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Part 1 of the Q DAC DC offset control. This part is a 1.15 signed max number and is combined with part 2 (1.4 signed max number) to form a 1.19 signed max DC offset value.Register 0x138 (MSB) and Register 0x139 (LSB) together set the 16 bit twos complement DC offset value for the Q DAC with a max value of 1.15.  The page index value in Register 0x08 dictates which Dual Q DAC will be programmed.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>QPATH_DC_OFFSET_1PART1</Name>
		<Address>0x139</Address>
		<Description>QPATH_DC_OFFSET_1PART1</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>QPATH_DC_OFFSET_1PART[15:8]</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>QPATH_DC_OFFSET_1PART[15:8]</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Part 1 of the Q DAC DC offset control. This part is a 1.15 signed max number and is combined with part 2 (1.4 signed max number) to form a 1.19 signed max DC offset value.Register 0x138 (MSB) and Register 0x139 (LSB) together set the 16 bit twos complement DC offset value for the Q DAC with a max value of 1.15.  The page index value in Register 0x08 dictates which Dual Q DAC will be programmed.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>IPATH_DC_OFFSET_2PART</Name>
		<Address>0x13A</Address>
		<Description>IPATH_DC_OFFSET_2PART</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>IPATH_DC_OFFSET_2PART</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>SIXTEENTH_OFFSET_I</Description>
				<Visibility>Public</Visibility>
				<Width>5</Width>
				<Notes>Part 2 of the I DAC DC offset control. This part is a 1.4 signed max number and is combined with part 1 (1.15 signed max number) to form a 1.19 signed max DC offset value.This part controls the fractional LSB mode to determine the increment value of the DC offset control in Register 0x136 and Register 0x137.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>5</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>QPATH_DC_OFFSET_2PART</Name>
		<Address>0x13B</Address>
		<Description>QPATH_DC_OFFSET_2PART</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>QPATH_DC_OFFSET_2PART</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>SIXTEENTH_OFFSET_Q</Description>
				<Visibility>Public</Visibility>
				<Width>5</Width>
				<Notes>Part 2 of the Q DAC DC offset control. This part is a 1.4 signed max number and is combined with part 1 (1.15 signed max number) to form a 1.19 signed max DC offset value.This part controls the fractional LSB mode to determine the increment value of the DC offset control in Register 0x138 and Register 0x139.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>5</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>IDAC_DIG_GAIN0</Name>
		<Address>0x13C</Address>
		<Description>IDAC_DIG_GAIN0</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>IDAC_DIG_GAIN[7:0]</Name>
				<Access>R/W</Access>
				<DefaultValue>234</DefaultValue>
				<Description>IDAC_DIG_GAIN[7:0]</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>I DAC digital gain.Register 0x13D bits [3:0] (MSB) and Register 0x13C bits [7:0] (LSB) together set the 12 bit digital gain value for the I DAC with gain range from 0 to 2x.  The page index value in Register 0x08 dictates which Dual I DAC will be programmed.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>IDAC_DIG_GAIN1</Name>
		<Address>0x13D</Address>
		<Description>IDAC_DIG_GAIN1</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>IDAC_DIG_GAIN[11:8]</Name>
				<Access>R/W</Access>
				<DefaultValue>10</DefaultValue>
				<Description>IDAC_DIG_GAIN[11:8]</Description>
				<Visibility>Public</Visibility>
				<Width>4</Width>
				<Notes>I DAC digital gain.Register 0x13D bits [3:0] (MSB) and Register 0x13C bits [7:0] (LSB) together set the 12 bit digital gain value for the I DAC with gain range from 0 to 2x.  The page index value in Register 0x08 dictates which Dual I DAC will be programmed.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>4</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>QDAC_DIG_GAIN0</Name>
		<Address>0x13E</Address>
		<Description>QDAC_DIG_GAIN0</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>QDAC_DIG_GAIN[7:0]</Name>
				<Access>R/W</Access>
				<DefaultValue>234</DefaultValue>
				<Description>QDAC_DIG_GAIN[7:0]</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Q DAC digital gain.Register 0x13F bits [3:0] (MSB) and Register 0x13E bits [7:0] (LSB) together set the 12 bit digital gain value for the Q DAC with gain range from 0 to 2x.  The page index value in Register 0x08 dictates which Dual Q DAC will be programmed.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>QDAC_DIG_GAIN1</Name>
		<Address>0x13F</Address>
		<Description>QDAC_DIG_GAIN1</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>QDAC_DIG_GAIN[11:8]</Name>
				<Access>R/W</Access>
				<DefaultValue>10</DefaultValue>
				<Description>QDAC_DIG_GAIN[11:8]</Description>
				<Visibility>Public</Visibility>
				<Width>4</Width>
				<Notes>Q DAC digital gain.Register 0x13F bits [3:0] (MSB) and Register 0x13E bits [7:0] (LSB) together set the 12 bit digital gain value for the Q DAC with gain range from 0 to 2x.  The page index value in Register 0x08 dictates which Dual Q DAC will be programmed.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>4</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>GAIN_RAMP_UP_STEP0</Name>
		<Address>0x140</Address>
		<Description>GAIN_RAMP_UP_STEP0</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>GAIN_RAMP_UP_STEP[7:0]</Name>
				<Access>R/W</Access>
				<DefaultValue>4</DefaultValue>
				<Description>GAIN_RAMP_UP_STEP[7:0]</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Gain ramp up step.This bit controls the amplitude step size of the soft gain ramp up feature.  For this unsigned register value, the higher the value programmed the larger the ramp up step size will be and therefore the faster the output will reach its full-scale.  Similarly, the lower the value programmed the smaller the ramp up step size will be and will take the output longer to reach its full-scale.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>GAIN_RAMP_UP_STEP1</Name>
		<Address>0x141</Address>
		<Description>GAIN_RAMP_UP_STEP1</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>GAIN_RAMP_UP_STEP[11:8]</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>GAIN_RAMP_UP_STEP[11:8]</Description>
				<Visibility>Public</Visibility>
				<Width>4</Width>
				<Notes>Gain ramp up step.This bit controls the amplitude step size of the soft gain ramp up feature.  For this unsigned register value, the higher the value programmed the larger the ramp up step size will be and therefore the faster the output will reach its full-scale.  Similarly, the lower the value programmed the smaller the ramp up step size will be and will take the output longer to reach its full-scale.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>4</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>GAIN_RAMP_DOWN_STEP0</Name>
		<Address>0x142</Address>
		<Description>GAIN_RAMP_DOWN_STEP0</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>GAIN_RAMP_DOWN_STEP[7:0]</Name>
				<Access>R/W</Access>
				<DefaultValue>9</DefaultValue>
				<Description>GAIN_RAMP_DOWN_STEP[7:0]</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Gain ramp down step.This bit controls the amplitude step size of the soft gain ramp down feature.  For this unsigned register value, the higher the value programmed the larger the ramp down step size will be and therefore the faster the output will be clamped to zero.  Similarly, the lower the value programmed the smaller the ramp down step size will be and will take the output longer to reach zero.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>GAIN_RAMP_DOWN_STEP1</Name>
		<Address>0x143</Address>
		<Description>GAIN_RAMP_DOWN_STEP1</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>GAIN_RAMP_DOWN_STEP[11:8]</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>GAIN_RAMP_DOWN_STEP[11:8]</Description>
				<Visibility>Public</Visibility>
				<Width>4</Width>
				<Notes>Gain ramp down step.This bit controls the amplitude step size of the soft gain ramp down feature.  For this unsigned register value, the higher the value programmed the larger the ramp down step size will be and therefore the faster the output will be clamped to zero.  Similarly, the lower the value programmed the smaller the ramp down step size will be and will take the output longer to reach zero.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>4</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>BLSM_CTRL</Name>
		<Address>0x146</Address>
		<Description>DEVICE_CONFIG_REG_1</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>DEVICE_CONFIG_1</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>DEVICE_CONFIG_1</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes></Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>BLSM_STAT</Name>
		<Address>0x147</Address>
		<Description>BSM_STAT</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>SoftBlankRB</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>SOFTBLANKRB</Description>
				<Visibility>Public</Visibility>
				<Width>2</Width>
				<Notes>Blanking state</Notes>
				<Options>
					<Option>
						<Description>Data is fully blanked.</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Ramping from data process to full blanking.</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Ramping from fully blanked to data process.</Description>
						<Value>8</Value>
					</Option>
					<Option>
						<Description>Data is being processed.</Description>
						<Value>9</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>6</RegOffset>
				<SliceWidth>2</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>PRBS</Name>
		<Address>0x14B</Address>
		<Description>PRBS</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>PRBS_EN</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>PRBS_EN</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Enable PRBS checker</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>PRBS_RESET</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>PRBS_RESET</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Reset error counters</Notes>
				<Options>
					<Option>
						<Description>Normal operation.</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Reset counters.</Description>
						<Value>1</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>1</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>PRBS_MODE</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>PRBS_MODE</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Polynomial select</Notes>
				<Options>
					<Option>
						<Description>7bit: \sup{x}{7} + \sup{x}{6} + 1</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>15bit: \sup{x}{15} + \sup{x}{14} + 1</Description>
						<Value>1</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>2</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>PRBS_GOOD_I</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>PRBS_GOOD_I</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Good data indicator real channel</Notes>
				<Options>
					<Option>
						<Description>Incorrect sequence detected.</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Correct PRBS sequence detected.</Description>
						<Value>1</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>6</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>PRBS_GOOD_Q</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>PRBS_GOOD_Q</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Good data indicator imaginary channel</Notes>
				<Options>
					<Option>
						<Description>Incorrect sequence detected.</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Correct PRBS sequence detected.</Description>
						<Value>1</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>7</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>PRBS_ERROR_I</Name>
		<Address>0x14C</Address>
		<Description>PRBS_ERROR_I</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>PRBS_COUNT_I</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>PRBS_COUNT_I</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Error count value real channel</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>PRBS_ERROR_Q</Name>
		<Address>0x14D</Address>
		<Description>PRBS_ERROR_Q</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>PRBS_COUNT_Q</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>PRBS_COUNT_Q</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Error count value imaginary channel</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>DACPLLt4</Name>
		<Address>0x1B4</Address>
		<Description>DACPLLT4</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>vco_cal_offset</Name>
				<Access>R/W</Access>
				<DefaultValue>15</DefaultValue>
				<Description>VCO_CAL_OFFSET</Description>
				<Visibility>Public</Visibility>
				<Width>4</Width>
				<Notes>Starting offset for VCO calibration.See Lookup Tables for values associated with VCO Cal Offset.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>3</RegOffset>
				<SliceWidth>4</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>DACPLLt5</Name>
		<Address>0x1B5</Address>
		<Description>DACPLLT5</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>vco_var</Name>
				<Access>R/W</Access>
				<DefaultValue>3</DefaultValue>
				<Description>VCO_VAR</Description>
				<Visibility>Public</Visibility>
				<Width>4</Width>
				<Notes>Varactor KVO setting.See Lookup Tables for values associated with VCO Varactor Reference.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>4</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>DACPLLt6</Name>
		<Address>0x1B6</Address>
		<Description>DACPLLT6</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>vco_lvl_out</Name>
				<Access>R/W</Access>
				<DefaultValue>10</DefaultValue>
				<Description>VCO_LVL_OUT</Description>
				<Visibility>Public</Visibility>
				<Width>4</Width>
				<Notes>VCO amplitude control.See Lookup Tables for values associated with VCO Output Level.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>4</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>DACPLLtB</Name>
		<Address>0x1BB</Address>
		<Description>DACPLLTB</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>vco_bias_ref</Name>
				<Access>R/W</Access>
				<DefaultValue>4</DefaultValue>
				<Description>VCO_BIAS_REF</Description>
				<Visibility>Public</Visibility>
				<Width>3</Width>
				<Notes>VCO Bias control.See Lookup Tables for values associated with VCO Bias Reference.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>3</SliceWidth>
			</BitField>
			<BitField>
				<Name>vco_bias_tcf</Name>
				<Access>R/W</Access>
				<DefaultValue>1</DefaultValue>
				<Description>VCO_BIAS_TCF</Description>
				<Visibility>Public</Visibility>
				<Width>2</Width>
				<Notes>TempCo for VCO bias.See Lookup Tables for values associated with VCO Bias Temperature Coefficient.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>3</RegOffset>
				<SliceWidth>2</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>DACPLLtD</Name>
		<Address>0x1BD</Address>
		<Description>DACPLLTD</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>vco_cal_ref_tcf</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>VCO_CAL_REF_TCF</Description>
				<Visibility>Public</Visibility>
				<Width>3</Width>
				<Notes>TempCo for cal ref.This field sets the temperature coefficient of the current used to set the VCO band calibration reference voltage. This is a field referenced in the configuration table for the PLL found earlier in the datasheet.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>3</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>DACPLLt17</Name>
		<Address>0x1C4</Address>
		<Description>DEVICE_CONFIG_REG_2</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>vco_var_ref_tcf</Name>
				<Access>R/W</Access>
				<DefaultValue>51</DefaultValue>
				<Description>DEVICE_CONFIG_2</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Varactor Reference TempCo.This register applies temperature coefficient to the current generating the varactor reference. This is used in order to compensate temperature drift in the VCO.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>MASTER_PD</Name>
		<Address>0x200</Address>
		<Description>MASTER_PD</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>spi_pd_master</Name>
				<Access>R/W</Access>
				<DefaultValue>1</DefaultValue>
				<Description>POWER DOWN JESD RX ANALOG</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Power down the entire JESD receiver analog (all eight channels plus bias).</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>PHY_PD</Name>
		<Address>0x201</Address>
		<Description>PHY_PD</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>spi_pd_phy</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>SPI_PD_PHY</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>SPI override to power down the individual PHYs. 
Bit 0 controls the SERDIN0+- PHY.
Bit 1 controls the SERDIN1+- PHY.
Bit 2 controls the SERDIN2+- PHY.
Bit 3 controls the SERDIN3+- PHY.
Bit 4 controls the SERDIN4+- PHY.
Bit 5 controls the SERDIN5+- PHY.
Bit 6 controls the SERDIN6+- PHY.
Bit 7 controls the SERDIN7+- PHY.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>GENERIC_PD</Name>
		<Address>0x203</Address>
		<Description>GENERIC_PD</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>spi_sync2_pd</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>POWER DOWN SYNCOUT1B+-</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Power down LVDS buffer for \overline{SYNCOUT1+-}.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>spi_sync1_pd</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>POWER DOWN SYNCOUT0B+-</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Power down LVDS buffer for \overline{SYNCOUT0+-}.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>1</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>CDR_RESET</Name>
		<Address>0x206</Address>
		<Description>CDR_RESET</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>spi_cdr_resetn</Name>
				<Access>R/W</Access>
				<DefaultValue>1</DefaultValue>
				<Description>SPI_CDR_RESETN</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Resets the digital control logic for all PHYs.</Notes>
				<Options>
					<Option>
						<Description>CDR logic is reset</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>CDR logic is operational</Description>
						<Value>1</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>CDR_OPERATING_MODE_REG_0</Name>
		<Address>0x230</Address>
		<Description>CDR_OPERATING_MODE_REG_0</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>spi_division_rate</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>CDR_OVERSAMP</Description>
				<Visibility>Public</Visibility>
				<Width>2</Width>
				<Notes>Enables oversampling of the input data.</Notes>
				<Options>
					<Option>
						<Description>No division.  2.83 Gbps &lt;= lane rate.</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Division by 2.  1.42 Gbps &lt;= lane rate &lt;= 2.76 Gbps.</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Division by 4.  750 Mbps &lt; Data rate &lt;= 1.5 Gbps.</Description>
						<Value>8</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>1</RegOffset>
				<SliceWidth>2</SliceWidth>
			</BitField>
			<BitField>
				<Name>spi_enhalfrate</Name>
				<Access>R/W</Access>
				<DefaultValue>1</DefaultValue>
				<Description>ENHALFRATE</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Enables half-rate CDR operation. Must be enabled for data rates above 5.65Gbps.</Notes>
				<Options>
					<Option>
						<Description>Disables CDR half rate operation, data rate &lt;= 5.52 Gbps.</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Enables CDR half rate operation, data rate &gt; 5.65 Gbps.</Description>
						<Value>1</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>5</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>CDR_OPERATING_MODE_REG_2</Name>
		<Address>0x232</Address>
		<Description>DEVICE_CONFIG_REG_3</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>spi_par_clk_edge</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>DEVICE_CONFIG_3</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Adjusts which output clock edge the output data is aligned to. Can be used to try to resolve digital timing errors between the analog and digital blocks.</Notes>
				<Options>
					<Option>
						<Description>This transition in the CDR's output data coincides with the falling edge of out_clk</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>This transition in the CDR's output data coincides with the rising edge of out_clk</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>0xFF:  Required register setting</Description>
						<Value>255</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>EQ_BIAS_REG</Name>
		<Address>0x268</Address>
		<Description>EQ_BIAS_REG</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>spi_eq_extra_spi_LSbits</Name>
				<Access>R/W</Access>
				<DefaultValue>1</DefaultValue>
				<Description>EQ_POWER_MODE</Description>
				<Visibility>Public</Visibility>
				<Width>2</Width>
				<Notes>Used to control the equalizer power / insertion loss capability</Notes>
				<Options>
					<Option>
						<Description>Normal mode.</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Low power mode.</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Invalid.</Description>
						<Value>8</Value>
					</Option>
					<Option>
						<Description>Invalid.</Description>
						<Value>9</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>6</RegOffset>
				<SliceWidth>2</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>SERDESPLL_ENABLE_CNTRL</Name>
		<Address>0x280</Address>
		<Description>SERDESPLL_ENABLE_CNTRL</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>spi_enable_synth</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>ENABLE_SERDESPLL</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Enable the SERDES PLL.
Setting this bit turns on all currents and calibrates the PLL.
Ensure the reference clock and division ratios are correct before enabling this bit.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>spi_recal_synth</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>RECAL_SERDESPLL</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Set this bit high to rerun all of the SERDES PLL calibration routines. Calibration is rising edge triggered, this bit must toggle from 0 to 1 for a calibration to occur.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>2</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>PLL_STATUS</Name>
		<Address>0x281</Address>
		<Description>PLL_STATUS</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>spi_pll_lock_rb</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>SERDES_PLL_LOCK_RB</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>If set, the synthesizer locked in the number of clock cycles set by lock detect count.</Notes>
				<Options>
					<Option>
						<Description>PLL is not locked.</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>PLL is locked.</Description>
						<Value>1</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>spi_cp_cal_valid_rb</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>SERDES_PLL_CAL_VALID_RB</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>This bit tells the user whether the charge pump calibration is completed.</Notes>
				<Options>
					<Option>
						<Description>Charge pump calibration is not valid.</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Charge pump calibration is valid.</Description>
						<Value>1</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>3</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>spi_cp_over_range_low_rb</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>SERDES_PLL_OVERRANGE_L</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Applies if spi_vco_output_level=0.  If set, the CP output is below "CP Level Threshold Low"</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>4</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>spi_cp_over_range_high_rb</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>SERDES_PLL_OVERRANGE_H</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Applies if spi_vco_output_level=0.  If set, the CP output is above "CP Level Threshold High"</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>5</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>REF_CLK_DIVIDER_LDO</Name>
		<Address>0x289</Address>
		<Description>REF_CLK_DIVIDER_LDO</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>spi_cdr_oversamp</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>SERDES_PLL_DIV_MODE</Description>
				<Visibility>Public</Visibility>
				<Width>2</Width>
				<Notes>Enable oversampling of input data in full rate mode. The valid options are 1x, 2x, and 4x.
Oversampling set in Register 0x230</Notes>
				<Options>
					<Option>
						<Description>1x works for half rate: 5.65Gbps to 10.64Gbps.</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>2x works for full rate: 2.83Gbps to 5.52Gbps.</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>4x works for full rate: 1.42Gbps to 2.76Gbps.</Description>
						<Value>8</Value>
					</Option>
					<Option>
						<Description>Invalid.</Description>
						<Value>9</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>2</SliceWidth>
			</BitField>
			<BitField>
				<Name>spi_ldo_bypass_filt</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>DEVICE_CONFIG_4</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Bypasses filter on LDO reference input.</Notes>
				<Options>
					<Option>
						<Description>Filter enabled.</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Filter bypassed.</Description>
						<Value>1</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>2</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>VCO_OUTPUT</Name>
		<Address>0x291</Address>
		<Description>DEVICE_CONFIG_REG_5</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>spi_vco_output_level</Name>
				<Access>R/W</Access>
				<DefaultValue>70</DefaultValue>
				<Description>DEVICE_CONFIG_5</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>These bits set the VCO output voltage level which sets the VCO phase noise performance and power consumption.  Range: 0.5V to 1.5V, step size = 67mV.  Normally set to 0xA</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>CP_LEVEL_DETECT</Name>
		<Address>0x29C</Address>
		<Description>DEVICE_CONFIG_REG_6</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>DEVICE_CONFIG6</Name>
				<Access>R/W</Access>
				<DefaultValue>23</DefaultValue>
				<Description>DEVICE_CONFIG_6-0</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>These bits set the low threshold for the CP level detector.  Range: Vdd-150mV to Vdd-500mV; resolution: -50mV/LSB.  All zeros = VDD - 150mV.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>VCO_VARACTOR_CONTROL_0</Name>
		<Address>0x29F</Address>
		<Description>DEVICE_CONFIG_REG_7</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>spi_vco_varactor_ref_tcf</Name>
				<Access>R/W</Access>
				<DefaultValue>51</DefaultValue>
				<Description>DEVICE_CONFIG_7</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>This is a temperature compensating voltage used to keep the RFPLL locked over temperature while maintaining a low Kv.  The varactor reference voltage attaches to the tune port of varactors that are not connected to the loop filter output.
Vvar-ref (T) = VDD - Vscale - Vtemp (T)</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>SPARE_REG_2</Name>
		<Address>0x2A4</Address>
		<Description>DEVICE_CONFIG_REG_8</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>spi_generic_spare_LSbits</Name>
				<Access>R/W</Access>
				<DefaultValue>75</DefaultValue>
				<Description>DEVICE_CONFIG_8</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Controls termination of the clock tree.
Bit [7] switches in 212 Ohms in termination near PHYs 1 and 6.
Bit [6] switches in 319 Ohms in termination near PHYs 1 and 6.
Bit [5] switches in 426 Ohms in termination near PHYs 1 and 6.
Bit [4] switches in 426 Ohms. in termination near PHYs 1 and 6.
Bit [3] switches in 212 Ohms in termination near PHYs 0 and 7.
Bit [2] switches in 319 Ohms in termination near PHYs 0 and 7.
Bit [1] switches in 426 Ohms in termination near PHYs 0 and 7.
Bit [0] switches in 426 Ohms. in termination near PHYs 0 and 7.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>SYNCOUTB_SWING</Name>
		<Address>0x2A5</Address>
		<Description>SYNCOUTB_SWING</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>spi_generic_spare_MSbits</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>SYNCOUTB_SWING_MD</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>These are spare bits, and are not currently used.</Notes>
				<Options>
					<Option>
						<Description>Normal Swing Mode</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>High Swing Mode</Description>
						<Value>1</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>TERM_BLK1_CTRLREG0</Name>
		<Address>0x2A7</Address>
		<Description>TERM_BLK1_CTRLREG0</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>spi_I_tune_r_cal_termblk1</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>RCAL_TERMBLK1</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>The rising edge of this bit starts a termination calibration routine.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>TERM_BLK1_CTRLREG3</Name>
		<Address>0x2AA</Address>
		<Description>DEVICE_CONFIG_REG_9</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>spi_I_slow_conductance_termblk1</Name>
				<Access>R/W</Access>
				<DefaultValue>195</DefaultValue>
				<Description>DEVICE_CONFIG_9</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Sets the expected conductance of the Slow skew.  This bounds the high-resistor end of the range.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>TERM_BLK1_CTRLREG4</Name>
		<Address>0x2AB</Address>
		<Description>DEVICE_CONFIG_REG_10</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>spi_I_fast_conductance_termblk1</Name>
				<Access>R/W</Access>
				<DefaultValue>147</DefaultValue>
				<Description>DEVICE_CONFIG_10</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Sets the expected conductance of the Fast skew.  This bounds the low-resistor end of the range.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>TERM_BLK2_CTRLREG0</Name>
		<Address>0x2AE</Address>
		<Description>TERM_BLK2_CTRLREG0</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>spi_I_tune_r_cal_termblk2</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>RCAL_TERMBLK2</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>The rising edge of this bit starts a termination calibration routine.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>TERM_BLK2_CTRLREG3</Name>
		<Address>0x2B1</Address>
		<Description>DEVICE_CONFIG_REG_11</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>spi_I_slow_conductance_termblk2</Name>
				<Access>R/W</Access>
				<DefaultValue>195</DefaultValue>
				<Description>DEVICE_CONFIG_11</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Sets the expected conductance of the Slow skew.  This bounds the high-resistor end of the range.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>TERM_BLK2_CTRLREG4</Name>
		<Address>0x2B2</Address>
		<Description>DEVICE_CONFIG_REG_12</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>spi_I_fast_conductance_termblk2</Name>
				<Access>R/W</Access>
				<DefaultValue>147</DefaultValue>
				<Description>DEVICE_CONFIG_12</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Sets the expected conductance of the Fast skew.  This bounds the low-resistor end of the range.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>GENERAL_JRX_CTRL_0</Name>
		<Address>0x300</Address>
		<Description>GENERAL_JRX_CTRL_0</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>link_en</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>LINK_EN</Description>
				<Visibility>Public</Visibility>
				<Width>2</Width>
				<Notes>Link enable. These bits bring up the JESD204B receiver digital circuitry: Bit[0] for Link 0 and Bit[1] for Link 1. 
Enable the link only after the following has occurred: 
1. All JESD204B parameters are set. 
2. DAC PLL is enabled and locked (Register 0x084[1] = 1).
3. JESD204B PHY is enabled (Register 0x200 = 0x00) and calibrated (Register 0x281[2] = 0).</Notes>
				<Options>
					<Option>
						<Description>Disable both JESD Link 1 and JESD Link 0.</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Disable JESD Link 1, enable JESD Link 0.</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Enable JESD Link 1, disable JESD Link 0.</Description>
						<Value>2</Value>
					</Option>
					<Option>
						<Description>Enable both JESD Link 1 and JESD Link 0.</Description>
						<Value>3</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>2</SliceWidth>
			</BitField>
			<BitField>
				<Name>sel_reg_map_1</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>LINK_PAGE</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Link register map selection. Allows the user to select which link register map to work with. For single link mode, set to 0.</Notes>
				<Options>
					<Option>
						<Description>Use Link 0 register map</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Use Link 1 register map</Description>
						<Value>1</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>2</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>link_mode</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>LINK_MODE</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Link Mode. 
This register selects either single link or dual link mode.</Notes>
				<Options>
					<Option>
						<Description>Single link mode.</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Dual link mode.</Description>
						<Value>1</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>3</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>checksum_mode</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>CHECKSUM_MODE</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Checksum mode. This bit controls the locally generated JESD204B link parameter checksum method. The value is stored in the FCMP registers (Register 0x40E, Register 0x416, Register 0x41E, Register 0x426, Register 0x42E, Register 0x436, Register 0x43E, and Register 0x446).</Notes>
				<Options>
					<Option>
						<Description>Checksum is calculated by summing the individual fields in the link configuration table as defined in Section 8.3, Table 20 of the JESD204B standard.</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Checksum is calculated by summing the registers containing the packed link configuration fields (SUM[0x450:0x45C] modulo 256).</Description>
						<Value>1</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>6</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>GENERAL_JRX_CTRL_1</Name>
		<Address>0x301</Address>
		<Description>GENERAL_JRX_CTRL_1</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>SUBCLASSV_local</Name>
				<Access>R/W</Access>
				<DefaultValue>1</DefaultValue>
				<Description>SUBCLASSV_LOCAL</Description>
				<Visibility>Public</Visibility>
				<Width>3</Width>
				<Notes>JESD204B subclass.</Notes>
				<Options>
					<Option>
						<Description>Subclass 0.</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Subclass 1.</Description>
						<Value>1</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>3</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>DYN_LINK_LATENCY_0</Name>
		<Address>0x302</Address>
		<Description>DYN_LINK_LATENCY_0</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>dyn_link_latency_0</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>DYN_LINK_LATENCY_0</Description>
				<Visibility>Public</Visibility>
				<Width>5</Width>
				<Notes>Dynamic link latency: Link 0.
Latency between the local LMFC (delayed from the global LMFC by the LMFC_DELAY setting) and the last arriving LMFC boundary (decoded from the data lane) in units of PCLK cycles. See the Deterministic Latency section.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>5</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>DYN_LINK_LATENCY_1</Name>
		<Address>0x303</Address>
		<Description>DYN_LINK_LATENCY_1</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>dyn_link_latency_1</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>DYN_LINK_LATENCY_1</Description>
				<Visibility>Public</Visibility>
				<Width>5</Width>
				<Notes>Dynamic link latency: Link 1.
Latency between the local LMFC (delayed from the global LMFC by the LMFC_DELAY setting) and the last arriving LMFC boundary (decoded from the data lane) in units of PCLK cycles. See the Deterministic Latency section.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>5</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>LMFC_DELAY_0</Name>
		<Address>0x304</Address>
		<Description>LMFC_DELAY_0</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>LMFC_delay_0</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>LMFC_DELAY_0</Description>
				<Visibility>Public</Visibility>
				<Width>5</Width>
				<Notes>LMFC delay: Link 0.
Delay in units of frame clock cycles from the global LMFC to the local LMFC for Link 0.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>5</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>LMFC_DELAY_1</Name>
		<Address>0x305</Address>
		<Description>LMFC_DELAY_1</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>LMFC_delay_1</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>LMFC_DELAY_1</Description>
				<Visibility>Public</Visibility>
				<Width>5</Width>
				<Notes>LMFC delay: Link 1.
Delay in units of frame clock cycles from the global LMFC to the local LMFC for Link 1.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>5</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>LMFC_VAR_0</Name>
		<Address>0x306</Address>
		<Description>LMFC_VAR_0</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>lmfc_var_0</Name>
				<Access>R/W</Access>
				<DefaultValue>6</DefaultValue>
				<Description>LMFC_VAR_0</Description>
				<Visibility>Public</Visibility>
				<Width>5</Width>
				<Notes>Location in RX LMFC where JESD words are read out from buffer.
This setting should not be more than 10.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>5</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>LMFC_VAR_1</Name>
		<Address>0x307</Address>
		<Description>LMFC_VAR_1</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>lmfc_var_1</Name>
				<Access>R/W</Access>
				<DefaultValue>6</DefaultValue>
				<Description>LMFC_VAR_1</Description>
				<Visibility>Public</Visibility>
				<Width>5</Width>
				<Notes>Location in RX LMFC where JESD words are read out from buffer.
This setting should not be more than 10.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>5</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>XBAR_LN_0_1</Name>
		<Address>0x308</Address>
		<Description>XBAR_LN_0_1</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>src_lane0</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>LOGICAL_LANE0_SRC</Description>
				<Visibility>Public</Visibility>
				<Width>3</Width>
				<Notes>Logic Lane 0 source. 
Select data from a PHY lane to use it for Logic Lane 0.</Notes>
				<Options>
					<Option>
						<Description>Data is from SERDIN0</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Data is from SERDIN1</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Data is from SERDIN2</Description>
						<Value>8</Value>
					</Option>
					<Option>
						<Description>Data is from SERDIN3</Description>
						<Value>9</Value>
					</Option>
					<Option>
						<Description>Data is from SERDIN4</Description>
						<Value>64</Value>
					</Option>
					<Option>
						<Description>Data is from SERDIN5</Description>
						<Value>65</Value>
					</Option>
					<Option>
						<Description>Data is from SERDIN6</Description>
						<Value>72</Value>
					</Option>
					<Option>
						<Description>Data is from SERDIN7</Description>
						<Value>73</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>3</SliceWidth>
			</BitField>
			<BitField>
				<Name>src_lane1</Name>
				<Access>R/W</Access>
				<DefaultValue>1</DefaultValue>
				<Description>LOGICAL_LANE1_SRC</Description>
				<Visibility>Public</Visibility>
				<Width>3</Width>
				<Notes>Logic Lane 1 source. 
Select data from a PHY lane to use it for Logic Lane 1.</Notes>
				<Options>
					<Option>
						<Description>Data is from SERDIN0</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Data is from SERDIN1</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Data is from SERDIN2</Description>
						<Value>8</Value>
					</Option>
					<Option>
						<Description>Data is from SERDIN3</Description>
						<Value>9</Value>
					</Option>
					<Option>
						<Description>Data is from SERDIN4</Description>
						<Value>64</Value>
					</Option>
					<Option>
						<Description>Data is from SERDIN5</Description>
						<Value>65</Value>
					</Option>
					<Option>
						<Description>Data is from SERDIN6</Description>
						<Value>72</Value>
					</Option>
					<Option>
						<Description>Data is from SERDIN7</Description>
						<Value>73</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>3</RegOffset>
				<SliceWidth>3</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>XBAR_LN_2_3</Name>
		<Address>0x309</Address>
		<Description>XBAR_LN_2_3</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>src_lane2</Name>
				<Access>R/W</Access>
				<DefaultValue>2</DefaultValue>
				<Description>LOGICAL_LANE2_SRC</Description>
				<Visibility>Public</Visibility>
				<Width>3</Width>
				<Notes>Logic Lane 2 source.
Select data from a PHY lane to use it for Logic Lane 2.</Notes>
				<Options>
					<Option>
						<Description>Data is from SERDIN0</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Data is from SERDIN1</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Data is from SERDIN2</Description>
						<Value>8</Value>
					</Option>
					<Option>
						<Description>Data is from SERDIN3</Description>
						<Value>9</Value>
					</Option>
					<Option>
						<Description>Data is from SERDIN4</Description>
						<Value>64</Value>
					</Option>
					<Option>
						<Description>Data is from SERDIN5</Description>
						<Value>65</Value>
					</Option>
					<Option>
						<Description>Data is from SERDIN6</Description>
						<Value>72</Value>
					</Option>
					<Option>
						<Description>Data is from SERDIN7</Description>
						<Value>73</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>3</SliceWidth>
			</BitField>
			<BitField>
				<Name>src_lane3</Name>
				<Access>R/W</Access>
				<DefaultValue>3</DefaultValue>
				<Description>LOGICAL_LANE3_SRC</Description>
				<Visibility>Public</Visibility>
				<Width>3</Width>
				<Notes>Logic Lane 3 source.
Select data from a PHY lane to use it for Logic Lane 3.</Notes>
				<Options>
					<Option>
						<Description>Data is from SERDIN0</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Data is from SERDIN1</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Data is from SERDIN2</Description>
						<Value>8</Value>
					</Option>
					<Option>
						<Description>Data is from SERDIN3</Description>
						<Value>9</Value>
					</Option>
					<Option>
						<Description>Data is from SERDIN4</Description>
						<Value>64</Value>
					</Option>
					<Option>
						<Description>Data is from SERDIN5</Description>
						<Value>65</Value>
					</Option>
					<Option>
						<Description>Data is from SERDIN6</Description>
						<Value>72</Value>
					</Option>
					<Option>
						<Description>Data is from SERDIN7</Description>
						<Value>73</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>3</RegOffset>
				<SliceWidth>3</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>XBAR_LN_4_5</Name>
		<Address>0x30A</Address>
		<Description>XBAR_LN_4_5</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>src_lane4</Name>
				<Access>R/W</Access>
				<DefaultValue>4</DefaultValue>
				<Description>LOGICAL_LANE4_SRC</Description>
				<Visibility>Public</Visibility>
				<Width>3</Width>
				<Notes>Logic Lane 4 source.
Select data from a PHY lane to use it for Logic Lane 4.</Notes>
				<Options>
					<Option>
						<Description>Data is from SERDIN0</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Data is from SERDIN1</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Data is from SERDIN2</Description>
						<Value>8</Value>
					</Option>
					<Option>
						<Description>Data is from SERDIN3</Description>
						<Value>9</Value>
					</Option>
					<Option>
						<Description>Data is from SERDIN4</Description>
						<Value>64</Value>
					</Option>
					<Option>
						<Description>Data is from SERDIN5</Description>
						<Value>65</Value>
					</Option>
					<Option>
						<Description>Data is from SERDIN6</Description>
						<Value>72</Value>
					</Option>
					<Option>
						<Description>Data is from SERDIN7</Description>
						<Value>73</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>3</SliceWidth>
			</BitField>
			<BitField>
				<Name>src_lane5</Name>
				<Access>R/W</Access>
				<DefaultValue>5</DefaultValue>
				<Description>LOGICAL_LANE5_SRC</Description>
				<Visibility>Public</Visibility>
				<Width>3</Width>
				<Notes>Logic Lane 5 source.
Select data from a PHY lane to use it for Logic Lane 5.</Notes>
				<Options>
					<Option>
						<Description>Data is from SERDIN0</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Data is from SERDIN1</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Data is from SERDIN2</Description>
						<Value>8</Value>
					</Option>
					<Option>
						<Description>Data is from SERDIN3</Description>
						<Value>9</Value>
					</Option>
					<Option>
						<Description>Data is from SERDIN4</Description>
						<Value>64</Value>
					</Option>
					<Option>
						<Description>Data is from SERDIN5</Description>
						<Value>65</Value>
					</Option>
					<Option>
						<Description>Data is from SERDIN6</Description>
						<Value>72</Value>
					</Option>
					<Option>
						<Description>Data is from SERDIN7</Description>
						<Value>73</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>3</RegOffset>
				<SliceWidth>3</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>XBAR_LN_6_7</Name>
		<Address>0x30B</Address>
		<Description>XBAR_LN_6_7</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>src_lane6</Name>
				<Access>R/W</Access>
				<DefaultValue>6</DefaultValue>
				<Description>LOGICAL_LANE6_SRC</Description>
				<Visibility>Public</Visibility>
				<Width>3</Width>
				<Notes>Logic Lane 6 source.
Select data from a PHY lane to use it for Logic Lane 6.</Notes>
				<Options>
					<Option>
						<Description>Data is from SERDIN0</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Data is from SERDIN1</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Data is from SERDIN2</Description>
						<Value>8</Value>
					</Option>
					<Option>
						<Description>Data is from SERDIN3</Description>
						<Value>9</Value>
					</Option>
					<Option>
						<Description>Data is from SERDIN4</Description>
						<Value>64</Value>
					</Option>
					<Option>
						<Description>Data is from SERDIN5</Description>
						<Value>65</Value>
					</Option>
					<Option>
						<Description>Data is from SERDIN6</Description>
						<Value>72</Value>
					</Option>
					<Option>
						<Description>Data is from SERDIN7</Description>
						<Value>73</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>3</SliceWidth>
			</BitField>
			<BitField>
				<Name>src_lane7</Name>
				<Access>R/W</Access>
				<DefaultValue>7</DefaultValue>
				<Description>LOGICAL_LANE7_SRC</Description>
				<Visibility>Public</Visibility>
				<Width>3</Width>
				<Notes>Logic Lane 7 source.
Select data from a PHY lane to use it for Logic Lane 7.</Notes>
				<Options>
					<Option>
						<Description>Data is from SERDIN0</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Data is from SERDIN1</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Data is from SERDIN2</Description>
						<Value>8</Value>
					</Option>
					<Option>
						<Description>Data is from SERDIN3</Description>
						<Value>9</Value>
					</Option>
					<Option>
						<Description>Data is from SERDIN4</Description>
						<Value>64</Value>
					</Option>
					<Option>
						<Description>Data is from SERDIN5</Description>
						<Value>65</Value>
					</Option>
					<Option>
						<Description>Data is from SERDIN6</Description>
						<Value>72</Value>
					</Option>
					<Option>
						<Description>Data is from SERDIN7</Description>
						<Value>73</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>3</RegOffset>
				<SliceWidth>3</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>FIFO_STATUS_REG_0</Name>
		<Address>0x30C</Address>
		<Description>FIFO_STATUS_REG_0</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>lane_fifo_full</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>LANE_FIFO_FULL</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>FIFO full flags for each logic lane.
Bit 0 corresponds to FIFO full flag for Lane 0.
Bit 1 corresponds to FIFO full flag for Lane 1.
Bit 2 corresponds to FIFO full flag for Lane 2.
Bit 3 corresponds to FIFO full flag for Lane 3.
Bit 4 corresponds to FIFO full flag for Lane 4.
Bit 5 corresponds to FIFO full flag for Lane 5.
Bit 6 corresponds to FIFO full flag for Lane 6.
Bit 7 corresponds to FIFO full flag for Lane 7.
A full FIFO indicates an error in the JESD204B configuration or with a system clock.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>FIFO_STATUS_REG_1</Name>
		<Address>0x30D</Address>
		<Description>FIFO_STATUS_REG_1</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>lane_fifo_empty</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>LANE_FIFO_EMPTY</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>FIFO empty flags for each logic lane.
Bit 0 corresponds to FIFO empty flag for Lane 0.
Bit 1 corresponds to FIFO empty flag for Lane 1.
Bit 2 corresponds to FIFO empty flag for Lane 2.
Bit 3 corresponds to FIFO empty flag for Lane 3.
Bit 4 corresponds to FIFO empty flag for Lane 4.
Bit 5 corresponds to FIFO empty flag for Lane 5.
Bit 6 corresponds to FIFO empty flag for Lane 6.
Bit 7 corresponds to FIFO empty flag for Lane 7.
An empty FIFO indicates an error in the JESD204B configuration or with a system clock.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>SYNCB_GEN_1</Name>
		<Address>0x312</Address>
		<Description>SYNCB_GEN_1</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>syncb_err_dur</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>SYNCB_ERR_DUR</Description>
				<Visibility>Public</Visibility>
				<Width>3</Width>
				<Notes>Duration of \overline{SYNCOUT} low for the purpose of error reporting.
This is shared between \overline{SYNCOUT0} and \overline{SYNCOUT1}. 0 means 5 frame 9 octets.</Notes>
				<Options>
					<Option>
						<Description>1/2 PClock cycle</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>1 PClock cycle</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>2 PClock cycle</Description>
						<Value>2</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>4</RegOffset>
				<SliceWidth>3</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>SPI_SYNC_CTRL</Name>
		<Address>0x314</Address>
		<Description>SERDES_SPI_REG</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>SPI_SYNC_clk_sel</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>SERDES_SPI_CONFIG</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>This register select the source clock used to handoff SPI memory controls from the SPI controller to the QBD register map.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>PHY_PRBS_TEST_EN</Name>
		<Address>0x315</Address>
		<Description>PHY_PRBS_TEST_EN</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>PHY_test_en</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>PHY_TEST_EN</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>PHY test enable. 
Enables the PHY BER test by ungating the clocks.
Bit 0 corresponds to PHY test enable for Lane 0.
Bit 1 corresponds to PHY test enable for Lane 1.
Bit 2 corresponds to PHY test enable for Lane 2.
Bit 3 corresponds to PHY test enable for Lane 3.
Bit 4 corresponds to PHY test enable for Lane 4.
Bit 5 corresponds to PHY test enable for Lane 5.
Bit 6 corresponds to PHY test enable for Lane 6.
Bit 7 corresponds to PHY test enable for Lane 7.</Notes>
				<Options>
					<Option>
						<Description>PHY test disable.</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>PHY test enable.</Description>
						<Value>1</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>PHY_PRBS_TEST_CTRL</Name>
		<Address>0x316</Address>
		<Description>PHY_PRBS_TEST_CTRL</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>PHY_test_reset</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>PHY_TEST_RESET</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>PHY PRBS test reset. 
Resets the PHY PRBS test state machine and error counters.</Notes>
				<Options>
					<Option>
						<Description>Not reset.</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Reset.</Description>
						<Value>1</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>PHY_test_start</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>PHY_TEST_START</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>PHY PRBS test start. 
Starts and stops the PHY PRBS test.</Notes>
				<Options>
					<Option>
						<Description>Test not started.</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Test started.</Description>
						<Value>1</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>1</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>PHY_PRBS_pat_sel</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>PHY_PRBS_PAT_SEL</Description>
				<Visibility>Public</Visibility>
				<Width>2</Width>
				<Notes>PHY PRBS pattern select. 
Selects the PRBS pattern for PHY BER test.</Notes>
				<Options>
					<Option>
						<Description>PRBS7</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>PRBS15</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>PRBS31</Description>
						<Value>8</Value>
					</Option>
					<Option>
						<Description>Not used</Description>
						<Value>9</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>2</RegOffset>
				<SliceWidth>2</SliceWidth>
			</BitField>
			<BitField>
				<Name>PHY_src_err_cnt</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>PHY_SRC_ERR_CNT</Description>
				<Visibility>Public</Visibility>
				<Width>3</Width>
				<Notes>PHY error count source. 
Selects which PHY errors are being reported in Register 0x31A to Register 0x31C.</Notes>
				<Options>
					<Option>
						<Description>Report Lane 0 error count</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Report Lane 1 error count</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Report Lane 2 error count</Description>
						<Value>8</Value>
					</Option>
					<Option>
						<Description>Report Lane 3 error count</Description>
						<Value>9</Value>
					</Option>
					<Option>
						<Description>Report Lane 4 error count</Description>
						<Value>64</Value>
					</Option>
					<Option>
						<Description>Report Lane 5 error count</Description>
						<Value>65</Value>
					</Option>
					<Option>
						<Description>Report Lane 6 error count</Description>
						<Value>72</Value>
					</Option>
					<Option>
						<Description>Report Lane 7 error count</Description>
						<Value>73</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>4</RegOffset>
				<SliceWidth>3</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>PHY_PRBS_TEST_THRESHOLD_LObits</Name>
		<Address>0x317</Address>
		<Description>PHY_PRBS_TEST_THRESHOLD_LOBITS</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>PHY_PRBS_threshold[7:0]</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>PHY_PRBS_THRESHOLD[7:0]</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>PHY PRBS error threshold.
Sets the error flag for PHY PRBS test.
For any given lane, if the PRBS error count exceeds the PRBS error threshold, the corresponding bit in the PHY PRBS pass register (Address 0x31D) are set to 0.
Register 0x319: Bits [23:16] of the 24-bit threshold value.
Register 0x318: Bits [15:8] of the 24-bit threshold value.
Register 0x317: Bits [7:0] of the 24-bit threshold value.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>PHY_PRBS_TEST_THRESHOLD_MIDbits</Name>
		<Address>0x318</Address>
		<Description>PHY_PRBS_TEST_THRESHOLD_MIDBITS</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>PHY_PRBS_threshold[15:8]</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>PHY_PRBS_THRESHOLD[15:8]</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>PHY PRBS error threshold.
Sets the error flag for PHY PRBS test.
For any given lane, if the PRBS error count exceeds the PRBS error threshold, the corresponding bit in the PHY PRBS pass register (Address 0x31D) are set to 0.
Register 0x319: Bits [23:16] of the 24-bit threshold value.
Register 0x318: Bits [15:8] of the 24-bit threshold value.
Register 0x317: Bits [7:0] of the 24-bit threshold value.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>PHY_PRBS_TEST_THRESHOLD_HIbits</Name>
		<Address>0x319</Address>
		<Description>PHY_PRBS_TEST_THRESHOLD_HIBITS</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>PHY_PRBS_threshold[23:16]</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>PHY_PRBS_THRESHOLD[23:16]</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>PHY PRBS error threshold.
Sets the error flag for PHY PRBS test.
For any given lane, if the PRBS error count exceeds the PRBS error threshold, the corresponding bit in the PHY PRBS pass register (Address 0x31D) are set to 0.
Register 0x319: Bits [23:16] of the 24-bit threshold value.
Register 0x318: Bits [15:8] of the 24-bit threshold value.
Register 0x317: Bits [7:0] of the 24-bit threshold value.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>PHY_PRBS_TEST_ERRCNT_LObits</Name>
		<Address>0x31A</Address>
		<Description>PHY_PRBS_TEST_ERRCNT_LOBITS</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>PHY_PRBS_err_cnt[7:0]</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>PHY_PRBS_ERR_CNT[7:0]</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>PHY PRBS Error Count.
Reported PHY BERT error count from lane selected using Register 0x316[6:4].
Register 0x31C: Bits [23:16] of the 24-bit reported PHY BERT error count.
Register 0x31B: Bits [15:8] of the 24-bit reported PHY BERT error count.
Register 0x31A: Bits [7:0] of the 24-bit reported PHY BERT error count.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>PHY_PRBS_TEST_ERRCNT_MIDbits</Name>
		<Address>0x31B</Address>
		<Description>PHY_PRBS_TEST_ERRCNT_MIDBITS</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>PHY_PRBS_err_cnt[15:8]</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>PHY_PRBS_ERR_CNT[15:8]</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>PHY PRBS Error Count.
Reported PHY BERT error count from lane selected using Register 0x316[6:4].
Register 0x31C: Bits [23:16] of the 24-bit reported PHY BERT error count.
Register 0x31B: Bits [15:8] of the 24-bit reported PHY BERT error count.
Register 0x31A: Bits [7:0] of the 24-bit reported PHY BERT error count.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>PHY_PRBS_TEST_ERRCNT_HIbits</Name>
		<Address>0x31C</Address>
		<Description>PHY_PRBS_TEST_ERRCNT_HIBITS</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>PHY_PRBS_err_cnt[23:16]</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>PHY_PRBS_ERR_CNT[23:16]</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>PHY PRBS Error Count.
Reported PHY BERT error count from lane selected using Register 0x316[6:4].
Register 0x31C: Bits [23:16] of the 24-bit reported PHY BERT error count.
Register 0x31B: Bits [15:8] of the 24-bit reported PHY BERT error count.
Register 0x31A: Bits [7:0] of the 24-bit reported PHY BERT error count.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>PHY_PRBS_TEST_STATUS</Name>
		<Address>0x31D</Address>
		<Description>PHY_PRBS_TEST_STATUS</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>PHY_PRBS_pass</Name>
				<Access>R</Access>
				<DefaultValue>255</DefaultValue>
				<Description>PHY_PRBS_PASS</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>PHY PRBS test pass/fail. 
Reports PHY BERT pass/fail for each lane.
Bit 0 corresponds to PHY BERT pass/fail for Lane 0.
Bit 1 corresponds to PHY BERT pass/fail for Lane 1.
Bit 2 corresponds to PHY BERT pass/fail for Lane 2.
Bit 3 corresponds to PHY BERT pass/fail for Lane 3.
Bit 4 corresponds to PHY BERT pass/fail for Lane 4.
Bit 5 corresponds to PHY BERT pass/fail for Lane 5.
Bit 6 corresponds to PHY BERT pass/fail for Lane 6.
Bit 7 corresponds to PHY BERT pass/fail for Lane 7.</Notes>
				<Options>
					<Option>
						<Description>Fail: number of PRBS errors (Address 0x31A to Address 0x31C) &gt; PHY PRBS error threshold set in Address 0x317 to Address 0x319.</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Pass: number of PRBS errors (Address 0x31A to Address 0x31C) &lt; PHY PRBS error threshold set in Address 0x317 to Address 0x319.</Description>
						<Value>1</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>SHORT_TPL_TEST_0</Name>
		<Address>0x32C</Address>
		<Description>SHORT_TPL_TEST_0</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>short_tpl_test_en</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>SHORT_TPL_TEST_EN</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Short transport layer test enable.See the Subclass 0 Operation section of this document for details on how to perform this test.</Notes>
				<Options>
					<Option>
						<Description>Disable.</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Enable.</Description>
						<Value>1</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>short_tpl_test_reset</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>SHORT_TPL_TEST_RESET</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Short transport layer test reset.Resets the result of short transport layer test.</Notes>
				<Options>
					<Option>
						<Description>Not reset</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Reset</Description>
						<Value>1</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>1</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>short_tpl_M_sel</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>SHORT_TPL_DAC_SEL</Description>
				<Visibility>Public</Visibility>
				<Width>2</Width>
				<Notes>Short transport layer test DAC select.Selects which DAC to sample.</Notes>
				<Options>
					<Option>
						<Description>Sample from DAC 0.</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Sample from DAC 1.</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Sample from DAC 2.</Description>
						<Value>8</Value>
					</Option>
					<Option>
						<Description>Sample from DAC 3.</Description>
						<Value>9</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>2</RegOffset>
				<SliceWidth>2</SliceWidth>
			</BitField>
			<BitField>
				<Name>short_tpl_sp_sel</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>SHORT_TPL_SP_SEL</Description>
				<Visibility>Public</Visibility>
				<Width>2</Width>
				<Notes>Short transport layer sample select.Selects which sample to check from the DAC selected via Bits[3:2].</Notes>
				<Options>
					<Option>
						<Description>Sample 0.</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Sample 1.</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Sample 2.</Description>
						<Value>8</Value>
					</Option>
					<Option>
						<Description>Sample 3.</Description>
						<Value>9</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>4</RegOffset>
				<SliceWidth>2</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>SHORT_TPL_TEST_1</Name>
		<Address>0x32D</Address>
		<Description>SHORT_TPL_TEST_1</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>short_tpl_ref_sp_LSB</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>SHORT_TPL_REF_SP_LSB</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Short transport layer test reference, sample LSB. 
This is the lower eight bits of the expected DAC sample. It is used to compare with the received DAC sample at the output of the JESD204B receiver.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>SHORT_TPL_TEST_2</Name>
		<Address>0x32E</Address>
		<Description>SHORT_TPL_TEST_2</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>short_tpl_ref_sp_MSB</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>SHORT_TPL_REF_SP_MSB</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Short transport layer test reference, sample MSB. 
This is the upper eight bits of the expected DAC sample. It is used to compare with the received DAC sample at the output of the JESD204B receiver.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>SHORT_TPL_TEST_3</Name>
		<Address>0x32F</Address>
		<Description>SHORT_TPL_TEST_3</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>short_tpl_fail</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>SHORT_TPL_FAIL</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Short transport layer test fail. 
This bit shows whether the selected DAC sample matches the reference sample. If they match it is a test pass, otherwise it is a test fail.</Notes>
				<Options>
					<Option>
						<Description>Test pass.</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Test fail.</Description>
						<Value>1</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>DIG_GENERIC_SPARE1</Name>
		<Address>0x333</Address>
		<Description>DEVICE_CONFIG_REG_13</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>drdl_fifo_bypass</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>DEVICE_CONFIG_13</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>DRDL FIFO adds delay variation to JESD link. When DAC pair A and DAC pair B use same clock it is possible to bypass this FIFO.</Notes>
				<Options>
					<Option>
						<Description>Do not bypass DRDL FIFO</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Bypass DRDL FIFO</Description>
						<Value>1</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>JESD_BIT_INVERSE_CTRL</Name>
		<Address>0x334</Address>
		<Description>JESD_BIT_INVERSE_CTRL</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>jesd_bit_inverse</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>JESD_BIT_INVERSE</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Short transport layer test fail. 
This bit shows whether the selected DAC sample matches the reference sample. If they match it is a test pass, otherwise it is a test fail.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>did_reg</Name>
		<Address>0x400</Address>
		<Description>DID_REG</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>DID_rd</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>DID_RD</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Device identification number. 
Link information received on Lane 0 as specified in Section 8.3 of JESD204B.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>bid_reg</Name>
		<Address>0x401</Address>
		<Description>BID_REG</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>BID_rd</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>BID_RD</Description>
				<Visibility>Public</Visibility>
				<Width>4</Width>
				<Notes>Bank identification - extension to DID. 
Link information received on Lane 0 as specified in Section 8.3 of JESD204B.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>4</SliceWidth>
			</BitField>
			<BitField>
				<Name>ADJCNT_rd</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>ADJCNT_RD</Description>
				<Visibility>Public</Visibility>
				<Width>4</Width>
				<Notes>Adjustment resolution to DAC LMFC.
Link information received on Lane 0 as specified in Section 8.3 of JESD204B.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>4</RegOffset>
				<SliceWidth>4</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>lid0_reg</Name>
		<Address>0x402</Address>
		<Description>LID0_REG</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>LID0_rd</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>LID0_RD</Description>
				<Visibility>Public</Visibility>
				<Width>5</Width>
				<Notes>Lane identification for Lane 0. 
Link information received on Lane 0 as specified in Section 8.3 of JESD204B.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>5</SliceWidth>
			</BitField>
			<BitField>
				<Name>PHADJ_rd</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>PHADJ_RD</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Phase adjustment request to DAC. 
Link information received on Lane 0 as specified in Section 8.3 of JESD204B.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>5</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>ADJDIR_rd</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>ADJDIR_RD</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Direction to adjust DAC LMFC. 
Link information received on Lane 0 as specified in Section 8.3 of JESD204B.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>6</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>scr_l_reg</Name>
		<Address>0x403</Address>
		<Description>SCR_L_REG</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>L_rd</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>L-1_RD</Description>
				<Visibility>Public</Visibility>
				<Width>5</Width>
				<Notes>Number of lanes per converter device. 
Link information received on Lane 0 as specified in Section 8.3 of JESD204B.</Notes>
				<Options>
					<Option>
						<Description>One lane per converter device.</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Two lanes per converter device.</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Four lanes per converter device.</Description>
						<Value>3</Value>
					</Option>
					<Option>
						<Description>Four lanes per converter device.</Description>
						<Value>7</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>5</SliceWidth>
			</BitField>
			<BitField>
				<Name>SCR_rd</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>SCR_RD</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Transmit scrambling status.
Link information received on Lane 0 as specified in Section 8.3 of JESD204B.</Notes>
				<Options>
					<Option>
						<Description>Scrambling is disabled.</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Scrambling is enabled.</Description>
						<Value>1</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>7</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>f_reg</Name>
		<Address>0x404</Address>
		<Description>F_REG</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>F_rd</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>F-1_RD</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Number of octets per frame. 
Settings of 1, 2 and 4 octets per frame are valid. 
Link information received on Lane 0 as specified in Section 8.3 of JESD204B.</Notes>
				<Options>
					<Option>
						<Description>One octet per frame.</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Two octets per frame.</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Four octets per frame.</Description>
						<Value>3</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>k_reg</Name>
		<Address>0x405</Address>
		<Description>K_REG</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>K_rd</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>K-1_RD</Description>
				<Visibility>Public</Visibility>
				<Width>5</Width>
				<Notes>Number of frames per multiframe. 
Settings of 16 or 32 are valid.
Link information received on Lane 0 as specified in Section 8.3 of JESD204B.</Notes>
				<Options>
					<Option>
						<Description>16 frames per multiframe.</Description>
						<Value>15</Value>
					</Option>
					<Option>
						<Description>32 frames per multiframe.</Description>
						<Value>31</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>5</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>m_reg</Name>
		<Address>0x406</Address>
		<Description>M_REG</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>M_rd</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>M-1_RD</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Number of converters per device. 
Link information received on Lane 0 as specified in Section 8.3 of JESD204B. Must be 0, 1, or 3.</Notes>
				<Options>
					<Option>
						<Description>One converter per device.</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Two converters per device.</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Four converters per device.</Description>
						<Value>3</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>cs_n_reg</Name>
		<Address>0x407</Address>
		<Description>CS_N_REG</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>N_rd</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>N-1_RD</Description>
				<Visibility>Public</Visibility>
				<Width>5</Width>
				<Notes>Converter resolution. 
Link information received on Lane 0 as specified in Section 8.3 of JESD204B.
Converter resolution of 16.</Notes>
				<Options>
					<Option>
						<Description>Converter resolution of 16.</Description>
						<Value>15</Value>
					</Option>
					<Option>
						<Description>Converter resolution of 16.</Description>
						<Value>0</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>5</SliceWidth>
			</BitField>
			<BitField>
				<Name>CS_rd</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>CS_RD</Description>
				<Visibility>Public</Visibility>
				<Width>2</Width>
				<Notes>Number of control bits per sample. 
Link information received on Lane 0 as specified in Section 8.3 of JESD204B.
CS must be 0 set to.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>6</RegOffset>
				<SliceWidth>2</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>np_reg</Name>
		<Address>0x408</Address>
		<Description>NP_REG</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>Np_rd</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>NP-1_RD</Description>
				<Visibility>Public</Visibility>
				<Width>5</Width>
				<Notes>Total number of bits per sample. 
Link information received on Lane 0 as specified in Section 8.3 of JESD204B.</Notes>
				<Options>
					<Option>
						<Description>16 bits per sample.</Description>
						<Value>15</Value>
					</Option>
					<Option>
						<Description>Must bbe set to 0x0F.</Description>
						<Value>0</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>5</SliceWidth>
			</BitField>
			<BitField>
				<Name>SUBCLASSV_rd</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>SUBCLASSV_RD</Description>
				<Visibility>Public</Visibility>
				<Width>3</Width>
				<Notes>Device subclass version. 
Link information received on Lane 0 as specified in Section 8.3 of JESD204B.</Notes>
				<Options>
					<Option>
						<Description>Subclass 0</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Subclass 1</Description>
						<Value>1</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>5</RegOffset>
				<SliceWidth>3</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>s_reg</Name>
		<Address>0x409</Address>
		<Description>S_REG</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>S_rd</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>S-1_RD</Description>
				<Visibility>Public</Visibility>
				<Width>5</Width>
				<Notes>Number of samples per converter per frame cycle. 
Settings of one and two are valid. See Table 25 and Table 26.</Notes>
				<Options>
					<Option>
						<Description>One sample per converter per frame.</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Two samples per converter per frame.</Description>
						<Value>1</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>5</SliceWidth>
			</BitField>
			<BitField>
				<Name>JESDV_rd</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>JESDV_RD</Description>
				<Visibility>Public</Visibility>
				<Width>3</Width>
				<Notes>JESD204 version. 
Link information received on Lane 0 as specified in Section 8.3 of JESD204B.</Notes>
				<Options>
					<Option>
						<Description>JESD204A</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>JESD204B</Description>
						<Value>1</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>5</RegOffset>
				<SliceWidth>3</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>hd_cf_reg</Name>
		<Address>0x40A</Address>
		<Description>HD_CF_REG</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>CF_rd</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>CF_RD</Description>
				<Visibility>Public</Visibility>
				<Width>5</Width>
				<Notes>Number of control words per frame clock period per link.
Link information received on Lane 0 as specified in Section 8.3 of JESD204B.
Bits[4:0] must be set to 0.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>5</SliceWidth>
			</BitField>
			<BitField>
				<Name>HD_rd</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>HD_RD</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>High density format. 
See Section 5.1.3 of the JESD294B standard.</Notes>
				<Options>
					<Option>
						<Description>Low density mode.</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>High density mode: link information received on Lane 0 as specified in Section 8.3 of JESD204B.</Description>
						<Value>1</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>7</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>res1_reg</Name>
		<Address>0x40B</Address>
		<Description>RES1_REG</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>RES1_rd</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>RES1_RD</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Reserved Field 1. 
Link information received on Lane 0 as specified in Section 8.3 of JESD204B.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>res2_reg</Name>
		<Address>0x40C</Address>
		<Description>RES2_REG</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>RES2_rd</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>RES2_RD</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Reserved Field 2. 
Link information received on Lane 0 as specified in Section 8.3 of JESD204B.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>checksum_reg</Name>
		<Address>0x40D</Address>
		<Description>CHECKSUM_REG</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>FCHK0_rd</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>FCHK0_RD</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Checksum for Lane 0. 
Link information received on Lane 0 as specified in Section 8.3 of JESD204B.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>compsum0_reg</Name>
		<Address>0x40E</Address>
		<Description>COMPSUM0_REG</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>FCMP0_rd</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>FCMP0_RD</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Computed checksum for Lane 0. 
The JESD204B receiver computes the checksum of the link information received on Lane 0 as specified in Section 8.3 of JESD204B. The computation method is set by the CHECKSUM_MODE bit (Address 0x300[6]) and must match the likewise calculated checksum in Register 0x40D.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>lid1_reg</Name>
		<Address>0x412</Address>
		<Description>LID1_REG</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>LID1_rd</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>LID1_RD</Description>
				<Visibility>Public</Visibility>
				<Width>5</Width>
				<Notes>Lane identification for Lane 1.
Link information received on lane 0 as specified in section 8.3 of JESD204B.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>5</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>checksum1_reg</Name>
		<Address>0x415</Address>
		<Description>CHECKSUM1_REG</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>FCHK1_rd</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>FCHK1_RD</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>CHECKSUM for Lane 1.
Link information received on lane 0 as specified in section 8.3 of JESD204B.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>compsum1_reg</Name>
		<Address>0x416</Address>
		<Description>COMPSUM1_REG</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>FCMP1_rd</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>FCMP1_RD</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Computed checksum for Lane 1 (see the description for Register 0x40E).</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>lid2_reg</Name>
		<Address>0x41A</Address>
		<Description>LID2_REG</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>LID2_rd</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>LID2_RD</Description>
				<Visibility>Public</Visibility>
				<Width>5</Width>
				<Notes>Lane identification for Lane 2.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>5</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>checksum2_reg</Name>
		<Address>0x41D</Address>
		<Description>CHECKSUM2_REG</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>FCHK2_rd</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>FCHK2_RD</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Checksum for Lane 2.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>compsum2_reg</Name>
		<Address>0x41E</Address>
		<Description>COMPSUM2_REG</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>FCMP2_rd</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>FCMP2_RD</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Computed checksum for Lane 2 (see the description for Register 0x40E).</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>lid3_reg</Name>
		<Address>0x422</Address>
		<Description>LID3_REG</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>LID3_rd</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>LID3_RD</Description>
				<Visibility>Public</Visibility>
				<Width>5</Width>
				<Notes>Lane identification for Lane 3.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>5</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>checksum3_reg</Name>
		<Address>0x425</Address>
		<Description>CHECKSUM3_REG</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>FCHK3_rd</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>FCHK3_RD</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Checksum for Lane 3.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>compsum3_reg</Name>
		<Address>0x426</Address>
		<Description>COMPSUM3_REG</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>FCMP3_rd</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>FCMP3_RD</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Computed checksum for Lane 3 (see the description for Register 0x40E).</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>lid4_reg</Name>
		<Address>0x42A</Address>
		<Description>LID4_REG</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>LID4_rd</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>LID4_RD</Description>
				<Visibility>Public</Visibility>
				<Width>5</Width>
				<Notes>Lane identification for Lane 4.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>5</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>checksum4_reg</Name>
		<Address>0x42D</Address>
		<Description>CHECKSUM4_REG</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>FCHK4_rd</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>FCHK4_RD</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Checksum for Lane 4.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>compsum4_reg</Name>
		<Address>0x42E</Address>
		<Description>COMPSUM4_REG</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>FCMP4_rd</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>FCMP4_RD</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Computed checksum for Lane 4 (see the description for Register 0x40E).</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>lid5_reg</Name>
		<Address>0x432</Address>
		<Description>LID5_REG</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>LID5_rd</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>LID5_RD</Description>
				<Visibility>Public</Visibility>
				<Width>5</Width>
				<Notes>Lane identification for Lane 5.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>5</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>checksum5_reg</Name>
		<Address>0x435</Address>
		<Description>CHECKSUM5_REG</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>FCHK5_rd</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>FCHK5_RD</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Checksum for Lane 5.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>compsum5_reg</Name>
		<Address>0x436</Address>
		<Description>COMPSUM5_REG</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>FCMP5_rd</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>FCMP5_RD</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Computed checksum for Lane 5 (see the description for Register 0x40E).</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>lid6_reg</Name>
		<Address>0x43A</Address>
		<Description>LID6_REG</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>LID6_rd</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>LID6_RD</Description>
				<Visibility>Public</Visibility>
				<Width>5</Width>
				<Notes>Lane identification for Lane 6.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>5</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>checksum6_reg</Name>
		<Address>0x43D</Address>
		<Description>CHECKSUM6_REG</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>FCHK6_rd</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>FCHK6_RD</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Checksum for Lane 6.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>compsum6_reg</Name>
		<Address>0x43E</Address>
		<Description>COMPSUM6_REG</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>FCMP6_rd</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>FCMP6_RD</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Computed checksum for Lane 6 (see the description for Register 0x40E).</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>lid7_reg</Name>
		<Address>0x442</Address>
		<Description>LID7_REG</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>LID7_rd</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>LID7_RD</Description>
				<Visibility>Public</Visibility>
				<Width>5</Width>
				<Notes>Lane identification for Lane 7.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>5</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>checksum7_reg</Name>
		<Address>0x445</Address>
		<Description>CHECKSUM7_REG</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>FCHK7_rd</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>FCHK7_RD</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Checksum for Lane 7.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>compsum7_reg</Name>
		<Address>0x446</Address>
		<Description>COMPSUM7_REG</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>FCMP7_rd</Name>
				<Access>R</Access>
				<DefaultValue>0</DefaultValue>
				<Description>FCMP7_RD</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Computed checksum for Lane 7 (see the description for Register 0x40E).</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>ils_did</Name>
		<Address>0x450</Address>
		<Description>ILS_DID</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>DID</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>DID</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Device identification number.
Link information received on Lane 0 as specified in Section 8.3 of JESD204B.
Must be set to value read in Register 0x400.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>ils_bid</Name>
		<Address>0x451</Address>
		<Description>ILS_BID</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>BID</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>BID</Description>
				<Visibility>Public</Visibility>
				<Width>4</Width>
				<Notes>Bank identification - extension to DID. 
Link information received on Lane 0 as specified in Section 8.3 of JESD204B.
Must be set to value read in Register 0x401[3:0].</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>4</SliceWidth>
			</BitField>
			<BitField>
				<Name>ADJCNT</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>ADJCNT</Description>
				<Visibility>Public</Visibility>
				<Width>4</Width>
				<Notes>Adjustment resolution to DAC LMFC. 
Link information received on Lane 0 as specified in Section 8.3 of JESD204B.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>4</RegOffset>
				<SliceWidth>4</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>ils_lid0</Name>
		<Address>0x452</Address>
		<Description>ILS_LID0</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>LID0</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>LID0</Description>
				<Visibility>Public</Visibility>
				<Width>5</Width>
				<Notes>Lane identification for Lane 0.
Link information received on Lane 0 as specified in Section 8.3 of JESD204B.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>5</SliceWidth>
			</BitField>
			<BitField>
				<Name>PHADJ</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>PHADJ</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Phase adjustment request to DAC. 
Link information received on Lane 0 as specified in Section 8.3 of JESD204B.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>5</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>ADJDIR</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>ADJDIR</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Direction to adjust DAC LMFC. 
Link information received on Lane 0 as specified in Section 8.3 of JESD204B.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>6</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>ils_scr_l</Name>
		<Address>0x453</Address>
		<Description>ILS_SCR_L</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>L</Name>
				<Access>R/W</Access>
				<DefaultValue>3</DefaultValue>
				<Description>L-1</Description>
				<Visibility>Public</Visibility>
				<Width>5</Width>
				<Notes>Number of lanes per converter device.
Single link: 1, 2, 4 and 8 lanes per converter are valid settings.
Dual link: 1, 2 and 4 lanes per converter are valid settings.
See TABLE 26 and TABLE 27.</Notes>
				<Options>
					<Option>
						<Description>One lane per converter device.</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Two lanes per converter device.</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Four lanes per converter device.</Description>
						<Value>3</Value>
					</Option>
					<Option>
						<Description>Eight lanes per converter device.</Description>
						<Value>7</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>5</SliceWidth>
			</BitField>
			<BitField>
				<Name>SCR</Name>
				<Access>R/W</Access>
				<DefaultValue>1</DefaultValue>
				<Description>SCR</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Receiver descrambling enable.</Notes>
				<Options>
					<Option>
						<Description>Descrambling is disabled.</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Descrambling is enabled.</Description>
						<Value>1</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>7</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>ils_f</Name>
		<Address>0x454</Address>
		<Description>ILS_F</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>F</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>F-1</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Number of octets per lane per frame.
Settings of 1, 2 and 4 octets per frame are valid.</Notes>
				<Options>
					<Option>
						<Description>One octet per frame</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Two octets per frame</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Four octets per frame</Description>
						<Value>3</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>ils_k</Name>
		<Address>0x455</Address>
		<Description>ILS_K</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>K</Name>
				<Access>R/W</Access>
				<DefaultValue>31</DefaultValue>
				<Description>K-1</Description>
				<Visibility>Public</Visibility>
				<Width>5</Width>
				<Notes>Number of frames per multiframe.
Settings of 16 or 32 are valid. Must be set to 32 when F = 1 (Register 0x476).</Notes>
				<Options>
					<Option>
						<Description>16 frames per multiframe.</Description>
						<Value>15</Value>
					</Option>
					<Option>
						<Description>32 frames per multiframe.</Description>
						<Value>31</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>5</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>ils_m</Name>
		<Address>0x456</Address>
		<Description>ILS_M</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>M</Name>
				<Access>R/W</Access>
				<DefaultValue>1</DefaultValue>
				<Description>M-1</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Number of converters per device. 
Settings of one, two, and four are valid for single link mode. Settings of one and two are valid in dual link mode. See Table 25 and Table 26.</Notes>
				<Options>
					<Option>
						<Description>One converter per device.</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Two converters per device.</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Four converters per device.</Description>
						<Value>3</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>ils_cs_n</Name>
		<Address>0x457</Address>
		<Description>ILS_CS_N</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>N</Name>
				<Access>R/W</Access>
				<DefaultValue>15</DefaultValue>
				<Description>N-1</Description>
				<Visibility>Public</Visibility>
				<Width>5</Width>
				<Notes>Converter resolution.
Must be set to 16 (0x0F).</Notes>
				<Options>
					<Option>
						<Description>Converter resolution must be 16</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Converter resolution of 16.</Description>
						<Value>15</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>5</SliceWidth>
			</BitField>
			<BitField>
				<Name>CS</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>CS</Description>
				<Visibility>Public</Visibility>
				<Width>2</Width>
				<Notes>Number of control bits per sample.
Must be set to 0. Control bits are not supported.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>6</RegOffset>
				<SliceWidth>2</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>ils_np</Name>
		<Address>0x458</Address>
		<Description>ILS_NP</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>Np</Name>
				<Access>R/W</Access>
				<DefaultValue>15</DefaultValue>
				<Description>NP-1</Description>
				<Visibility>Public</Visibility>
				<Width>5</Width>
				<Notes>Total number of bits per sample.
Must be set to 16 (0x0F). Refer to TABLE 26 and TABLE 27.</Notes>
				<Options>
					<Option>
						<Description>Must be set to 0x0F</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>16 bits per sample.</Description>
						<Value>15</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>5</SliceWidth>
			</BitField>
			<BitField>
				<Name>SUBCLASSV</Name>
				<Access>R/W</Access>
				<DefaultValue>1</DefaultValue>
				<Description>SUBCLASSV</Description>
				<Visibility>Public</Visibility>
				<Width>3</Width>
				<Notes>Device subclass version.
Must be set to 1 (3'b001).</Notes>
				<Options>
					<Option>
						<Description>Subclass 0</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Subclass 1</Description>
						<Value>1</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>5</RegOffset>
				<SliceWidth>3</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>ils_s</Name>
		<Address>0x459</Address>
		<Description>ILS_S</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>S</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>S-1</Description>
				<Visibility>Public</Visibility>
				<Width>5</Width>
				<Notes>Number of samples per converter per frame cycle.
Settings of one and two are valid. Refer to TABLE 26 and TABLE 27.</Notes>
				<Options>
					<Option>
						<Description>One sample per converter per frame.</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Two samples per converter per frame.</Description>
						<Value>1</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>5</SliceWidth>
			</BitField>
			<BitField>
				<Name>JESDV</Name>
				<Access>R/W</Access>
				<DefaultValue>1</DefaultValue>
				<Description>JESDV</Description>
				<Visibility>Public</Visibility>
				<Width>3</Width>
				<Notes>JESD204 version.</Notes>
				<Options>
					<Option>
						<Description>JESD204A</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>JESD204B</Description>
						<Value>1</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>5</RegOffset>
				<SliceWidth>3</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>ils_hd_cf</Name>
		<Address>0x45A</Address>
		<Description>ILS_HD_CF</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>CF</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>CF</Description>
				<Visibility>Public</Visibility>
				<Width>5</Width>
				<Notes>Number of control words per frame clock period per link.
Must be set to 0. Control bits are not supported.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>5</SliceWidth>
			</BitField>
			<BitField>
				<Name>HD</Name>
				<Access>R/W</Access>
				<DefaultValue>1</DefaultValue>
				<Description>HD</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>High density format. If F = 1, HD must be set to 1.  Otherwise, HD must be set to 0.
See Section 5.1.3 of JESD204B standard.</Notes>
				<Options>
					<Option>
						<Description>Low density mode</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>High density mode</Description>
						<Value>1</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>7</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>ils_res1</Name>
		<Address>0x45B</Address>
		<Description>ILS_RES1</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>RES1</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>RES1</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Reserved Field 1</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>ils_res2</Name>
		<Address>0x45C</Address>
		<Description>ILS_RES2</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>RES2</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>RES2</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Reserved Field 2</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>ils_checksum</Name>
		<Address>0x45D</Address>
		<Description>ILS_CHECKSUM</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>FCHK0</Name>
				<Access>R/W</Access>
				<DefaultValue>69</DefaultValue>
				<Description>FCHK0</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Checksum for Lane 0. 
The checksum for the values programmed into Register 0x450 to Register 0x45C must be calculated according to Section 8.3 of the JESD204B specifications and written here (SUM[0x450:0x45C] modulo 256).</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>ErrCntrMon</Name>
		<Address>0x46B</Address>
		<Description>ERRCNTRMON</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>CntrSel</Name>
				<Access>W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>CNTRSEL</Description>
				<Visibility>Public</Visibility>
				<Width>2</Width>
				<Notes>JESD204B error counter select. 
Writing these bits allows the readback of the following JESD204B errors for the lane designated by the register write to LANESEL (Bits[6:4]). To read a counter value, the LANESEL and CNTRSEL are written first, then the readback accesses the desired counter.</Notes>
				<Options>
					<Option>
						<Description>BADDISCNTR: bad running disparity counter.</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>NITCNTR: not in table error counter.</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>UEKCCNTR: Unexpected /K/ character counter.</Description>
						<Value>8</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>2</SliceWidth>
			</BitField>
			<BitField>
				<Name>LaneSel</Name>
				<Access>W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>LANESEL</Description>
				<Visibility>Public</Visibility>
				<Width>3</Width>
				<Notes>Lane select for JESD204B error counter. 
Writing these bits selects the JESD204B lane to monitor the error type designated by the register write to CNTRSEL (Bits[1:0]). BADDISCNTR, NITCNTR and UEKCCNTR error counters in each lane are accessed via indirect addressing. To read a counter value, the LANESEL and CNTRSEL bits are first written, then the readback accesses the desired counter.</Notes>
				<Options>
					<Option>
						<Description>Selects Link Lane 0</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Selects Link Lane 1</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Selects Link Lane 2</Description>
						<Value>8</Value>
					</Option>
					<Option>
						<Description>Selects Link Lane 3</Description>
						<Value>9</Value>
					</Option>
					<Option>
						<Description>Selects Link Lane 4</Description>
						<Value>64</Value>
					</Option>
					<Option>
						<Description>Selects Link Lane 5</Description>
						<Value>65</Value>
					</Option>
					<Option>
						<Description>Selects Link Lane 6</Description>
						<Value>72</Value>
					</Option>
					<Option>
						<Description>Selects Link Lane 7</Description>
						<Value>73</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>4</RegOffset>
				<SliceWidth>3</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>LaneDeskew</Name>
		<Address>0x46C</Address>
		<Description>LANEDESKEW</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>LaneDeskew</Name>
				<Access>R/W</Access>
				<DefaultValue>15</DefaultValue>
				<Description>LANEDESKEW</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Lane deskew. 
Enabled on a per lane basis by writing 1 to the appropriate bit position: Bits[7:0] map to Lane 7 to Lane 0, respectively. Note that in dual link mode, only Bits[3:0] are used for each link.
XXXX XXX1 : Deskew enabled for lane 0
XXXX XX1X : Deskew enabled for lane 1
...	  ...
1XXX XXXX : Deskew enabled for lane 7</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>BadDisparity</Name>
		<Address>0x46D</Address>
		<Description>BADDISPARITY</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>Lane_Addr_Dis</Name>
				<Access>W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>LANE_ADDR_DIS</Description>
				<Visibility>Public</Visibility>
				<Width>3</Width>
				<Notes>Lane address for functions described in Bits[7:5].</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>3</SliceWidth>
			</BitField>
			<BitField>
				<Name>Rst_Err_Cntr_Dis</Name>
				<Access>W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>RST_ERR_CNTR_DIS</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Reset BADDIS error counter for lane selected via Bits[2:0] by writing 1 to this bit.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>5</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>Dis_Err_Cntr_Dis</Name>
				<Access>W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>DISABLE_ERR_CNTR_DIS</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Disable the BADDIS error counter for lane selected via Bits[2:0] by writing 1 to this bit.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>6</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>Rst_IRQ_Dis</Name>
				<Access>W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>RST_IRQ_DIS</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Reset BADDIS IRQ for lane selected via Bits[2:0] by writing 1 to this bit.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>7</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>NITDisparity</Name>
		<Address>0x46E</Address>
		<Description>NIT_W</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>Lane_Addr_NIT</Name>
				<Access>W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>LANE_ADDR_NIT</Description>
				<Visibility>Public</Visibility>
				<Width>3</Width>
				<Notes>Lane address for functions described in Bits[7:5].</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>3</SliceWidth>
			</BitField>
			<BitField>
				<Name>Rst_Err_Cntr_NIT</Name>
				<Access>W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>RST_ERR_CNTR_NIT</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Reset error counter for lane selected via Bits[2:0] by writing 1 to this bit.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>5</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>Dis_Err_Cntr_NIT</Name>
				<Access>W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>DISABLE_ERR_CNTR_NIT</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Disable the error counter for lane selected via Bits[2:0] by writing 1 to this bit.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>6</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>Rst_IRQ_NIT</Name>
				<Access>W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>RST_IRQ_NIT</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Reset IRQ for lane selected via Bits[2:0] by writing 1 to this bit.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>7</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>UnExpectedKchar</Name>
		<Address>0x46F</Address>
		<Description>UNEXPECTEDCONTROL_W</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>Lane_Addr_K</Name>
				<Access>W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>LANE_ADDR_UCC</Description>
				<Visibility>Public</Visibility>
				<Width>3</Width>
				<Notes>Lane address for functions described in Bits[7:5].</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>3</SliceWidth>
			</BitField>
			<BitField>
				<Name>Rst_Err_Cntr_K</Name>
				<Access>W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>RST_ERR_CNTR_UCC</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Reset error counter for lane selected via Bits[2:0] by writing 1 to this bit.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>5</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>Dis_Err_Cntr_K</Name>
				<Access>W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>DISABLE_ERR_CNTR_UCC</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Disable the error counter for lane selected via Bits[2:0] by writing 1 to this bit.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>6</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>Rst_IRQ_K</Name>
				<Access>W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>RST_IRQ_UCC</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Reset IRQ for lane selected via Bits[2:0] by writing 1 to this bit.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>7</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>CodeGrpSyncFlg</Name>
		<Address>0x470</Address>
		<Description>CODEGRPSYNCFLG</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>CodeGrpSync</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>CODEGRPSYNC</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Code group sync flag (from each instantiated lane).
Writing 1 to Bit 7 resets the IRQ. The associated IRQ flag is located in Register 0x47A[0].
A loss of CODEGRPSYNC triggers sync request assertion. See the \overline{SYNCOUT} and  SYSREF signal section and the Deterministic Latency section.</Notes>
				<Options>
					<Option>
						<Description>Synchronization lost.</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Synchronization achieved.</Description>
						<Value>1</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>FrameSyncFlg</Name>
		<Address>0x471</Address>
		<Description>FRAMESYNCFLG</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>FrameSync</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>FRAMESYNC</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Frame sync flag (from each instantiated lane).
This register indicates the live status for each lane.
Writing 1 to Bit 7 resets the IRQ.
A loss of frame sync automatically initiates a synchronization sequence.</Notes>
				<Options>
					<Option>
						<Description>Synchronization lost.</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Synchronization achieved.</Description>
						<Value>1</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>GoodChkSumFlg</Name>
		<Address>0x472</Address>
		<Description>GOODCHKSUMFLG</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>GoodCheckSum</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>GOODCHECKSUM</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Good checksum flag (from each instantiated lane). 
Writing 1 to Bit 7 resets the IRQ. The associated IRQ flag is located in Register 0x47A[2].</Notes>
				<Options>
					<Option>
						<Description>Last computed checksum is not correct.</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Last computed checksum is correct.</Description>
						<Value>1</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>InitLaneSyncFlg</Name>
		<Address>0x473</Address>
		<Description>INITLANESYNCFLG</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>InitialLaneSync</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>INITIALLANESYNC</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Initial lane sync flag (from each instantiated lane). 
Writing 1 to Bit 7 resets the IRQ. The associated IRQ flag is located in Register 0x47A[3].
Loss of synchronization is also reported on \overline{SYNCOUT1+-} or \overline{SYNCOUT0+-}. See the \overline{SYNCOUT} and SYSREF+- Signal section and the Deterministic Latency section.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>CTRLREG1</Name>
		<Address>0x476</Address>
		<Description>CTRLREG1</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>F_again</Name>
				<Access>R/W</Access>
				<DefaultValue>1</DefaultValue>
				<Description>F</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Number of octets per frame. (Not in F-1 format).
Settings of 1, 2, and 4 are valid. See TABLE 26 and TABLE 27.</Notes>
				<Options>
					<Option>
						<Description>One octet per frame.</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Two octets per frame.</Description>
						<Value>2</Value>
					</Option>
					<Option>
						<Description>Four octets per frame.</Description>
						<Value>4</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>CTRLREG2</Name>
		<Address>0x477</Address>
		<Description>CTRLREG2</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>auto_ecntr_rst</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>THRESHOLD_MASK_EN</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Auto error counter reset.</Notes>
				<Options>
					<Option>
						<Description>The error counter or counters causing a sync request are automatically reset.</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>the error counter(s) are not automatically reset</Description>
						<Value>0</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>3</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>ILAS_Mode</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>ILAS_MODE</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>ILAS test mode.
Defined in Section 5.3.3.8 of JESD204B specification.</Notes>
				<Options>
					<Option>
						<Description>JESD204B receiver is constantly receiving ILAS frames</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Normal link operation</Description>
						<Value>0</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>7</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>Kval</Name>
		<Address>0x478</Address>
		<Description>KVAL</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>Ksync</Name>
				<Access>R/W</Access>
				<DefaultValue>1</DefaultValue>
				<Description>KSYNC</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Number of 4 x K multiframes during ILAS.
Sets the number of multiframes to send lane alignment sequence during the initial lane alignment.</Notes>
				<Options>
					<Option>
						<Description>4 x K multiframes.</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>4 x K multiframes.</Description>
						<Value>1</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>IRQVector_mask</Name>
		<Address>0x47A</Address>
		<Description>IRQVECTOR_MASK</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>CodeGrpSync_mask</Name>
				<Access>W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>CODEGRPSYNC_MASK</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes></Notes>
				<Options>
					<Option>
						<Description>Code group sync state machine flag is masked.</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Code Group Sync interupt flag is passed to interupt</Description>
						<Value>1</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>FRAMESYNC_MASK</Name>
				<Access>W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>FRAMESYNC_MASK</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes></Notes>
				<Options>
					<Option>
						<Description>If frame sync (Register 0x471) fails on any lane, is pulled low.</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>[no description]</Description>
						<Value>0</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>1</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>BadCheckSum_mask</Name>
				<Access>W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>BADCHECKSUM_MASK</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes></Notes>
				<Options>
					<Option>
						<Description>Bad checksum flag is masked.</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Bad Check sum use for interupt</Description>
						<Value>1</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>2</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>InitialLaneSync_mask</Name>
				<Access>W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>INITIALLANESYNC_MASK</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes></Notes>
				<Options>
					<Option>
						<Description>Initial lane sync flag is masked.</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Initial Lane Sync used in interupt</Description>
						<Value>1</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>3</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>UEKC_mask</Name>
				<Access>W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>UCC_MASK</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes></Notes>
				<Options>
					<Option>
						<Description>Unexpected K character error count flag is masked.</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Unexpected K-character Error count triggers interupt</Description>
						<Value>1</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>5</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>NITD_mask</Name>
				<Access>W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>NIT_MASK</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes></Notes>
				<Options>
					<Option>
						<Description>Not in table disparity character error count flag is masked.</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Not In Table Disparity Character Error count flag triggers interupt</Description>
						<Value>1</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>6</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>BADDIS_mask</Name>
				<Access>W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>BADDIS_MASK</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Read the IRQ flag; write the IRQ enable mask for all lanes.</Notes>
				<Options>
					<Option>
						<Description>Bad disparity character error count flag is masked.</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Bad Disparity Character Error count flag trggers interupt</Description>
						<Value>1</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>7</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>SyncAssertionMask</Name>
		<Address>0x47B</Address>
		<Description>SYNCASSERTIONMASK</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>cmm_enable</Name>
				<Access>R/W</Access>
				<DefaultValue>1</DefaultValue>
				<Description>CMM_ENABLE</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Configuration mismatch IRQ enable.</Notes>
				<Options>
					<Option>
						<Description>Enables IRQ generation if a configuration mismatch is detected.</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Configuration mismatch IRQ disabled.</Description>
						<Value>0</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>3</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>Cmm</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>CMM</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Writing a 1 resets the cmm_irq (applicable if 0x47B[3]=1).Configuration mismatch flag when read.</Notes>
				<Options>
					<Option>
						<Description>Lane 0 configuration registers (Register 0x450 to Regis-ter 0x45D) do not match the comparable JESD204B transmit settings as reported in Register 0x400 to Register 0x40D.</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>Lane 0 configuration registers (0x450-0x45D) match the comparable JESD Tx settings as reported in 0x400-0x40D</Description>
						<Value>0</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>4</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>unex_K_s</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>UCC_S</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Unexpected K character error on sync.</Notes>
				<Options>
					<Option>
						<Description>The deframer asserts the \overline{SYNCOUTx+-} signal when the unexpected K character error count reaches the threshold in Register 0x47C.</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>The deframer will not assert the \overline{SYNCOUT} when the Unexpected K-character Error count reaches the threshold in reg. 0x47C</Description>
						<Value>0</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>5</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>nit_dis_s</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>NIT_S</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Not in table disparity character error on sync.</Notes>
				<Options>
					<Option>
						<Description>The deframer asserts the \overline{SYNCOUTx+-} signal when the not in table disparity character error count reaches the threshold in Register 0x47C.</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>The deframer will not assert the \overline{SYNCOUT} when the Not In Table Disparity character error count reaches the threshold on reg. 0x47C</Description>
						<Value>0</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>6</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
			<BitField>
				<Name>bad_dis_s</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>BADDIS_S</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Bad disparity error on sync.</Notes>
				<Options>
					<Option>
						<Description>The deframer asserts the \overline{SYNCOUTx+-} signal when the bad disparity error count reaches the threshold in Register 0x47C.</Description>
						<Value>1</Value>
					</Option>
					<Option>
						<Description>The deframer will not assert the \overline{SYNCOUT} when the Bad Disparity Error count reaches the threshold in reg. 0x47C</Description>
						<Value>0</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>7</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>ErrorThres</Name>
		<Address>0x47C</Address>
		<Description>ERRORTHRES</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>ETH</Name>
				<Access>R/W</Access>
				<DefaultValue>255</DefaultValue>
				<Description>ETH</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Error threshold.
Bad disparity, NIT disparity, and unexpected K character errors are counted and compared to the error threshold value. When the count is equal, either an IRQ is generated or the \overline{SYNCOUTx+-} signal is asserted per the mask register settings, or both. Function is performed in all lanes.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>LaneEnable</Name>
		<Address>0x47D</Address>
		<Description>LANEENABLE</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>Lane_ena</Name>
				<Access>R/W</Access>
				<DefaultValue>15</DefaultValue>
				<Description>LANE_ENA</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>Lane enable (1 bit per lane).
The register must be programmed before receiving the code group pattern for proper operation. The default value is only Lane 0 enabled.  Setting each bit high enables the lane for the active link, whereas setting each bit low disables the lane.</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>Ramp_Ena</Name>
		<Address>0x47E</Address>
		<Description>RAMP_ENA</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>Ena_Ramp_Check</Name>
				<Access>W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>ENA_RAMP_CHECK</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>Enable ramp checking at the beginning of ILAS</Notes>
				<Options>
					<Option>
						<Description>Disable ramp checking at beginning of ILAS; ILAS data need not be a ramp.</Description>
						<Value>0</Value>
					</Option>
					<Option>
						<Description>Enable ramp checking. ILAS data needs to be a ramp starting at 00-01-02; otherwise, the ramp ILAS fails and the device does not start up.</Description>
						<Value>1</Value>
					</Option>
				</Options>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>DIG_TEST0</Name>
		<Address>0x520</Address>
		<Description>DIG_TEST0</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>DC_TEST_MOD</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>DC_TEST_MODE</Description>
				<Visibility>Public</Visibility>
				<Width>1</Width>
				<Notes>fs/8 and decoder testing mode</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>1</RegOffset>
				<SliceWidth>1</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>DC_TEST_VALUEI0</Name>
		<Address>0x521</Address>
		<Description>DC_TEST_VALUEI0</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>TEST_DC_VALUEI[7:0]</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>TEST_DC_VALUEI[7:0]</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>DC value LSB of fs/8 and decoder testing for I DAC</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>DC_TEST_VALUEI1</Name>
		<Address>0x522</Address>
		<Description>DC_TEST_VALUEI1</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>TEST_DC_VALUEI[15:8]</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>TEST_DC_VALUEI[15:8]</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>DC value LSB of fs/8 and decoder testing for I DAC</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>DC_TEST_VALUEQ0</Name>
		<Address>0x523</Address>
		<Description>DC_TEST_VALUEQ0</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>TEST_DC_VALUEQ[7:0]</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>TEST_DC_VALUEQ[7:0]</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>DC value LSB of fs/8 and decoder testing for Q DAC</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
	<Register>
		<Name>DC_TEST_VALUEQ1</Name>
		<Address>0x524</Address>
		<Description>DC_TEST_VALUEQ1</Description>
		<Exists>True</Exists>
		<Width>8</Width>
		<Notes></Notes>
		<BitFields>
			<BitField>
				<Name>TEST_DC_VALUEQ[15:8]</Name>
				<Access>R/W</Access>
				<DefaultValue>0</DefaultValue>
				<Description>TEST_DC_VALUEQ[15:8]</Description>
				<Visibility>Public</Visibility>
				<Width>8</Width>
				<Notes>DC value LSB of fs/8 and decoder testing for Q DAC</Notes>
				<BitOffset>0</BitOffset>
				<RegOffset>0</RegOffset>
				<SliceWidth>8</SliceWidth>
			</BitField>
		</BitFields>
	</Register>
</ad9144>