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skx_server_ratios.py
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skx_server_ratios.py
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#
# auto generated TopDown/TMAM 4.19-full-perf description for Intel Xeon Scalable Processors (code named Skylake Server)
# Please see http://ark.intel.com for more details on these CPUs.
#
# References:
# http://bit.ly/tma-ispass14
# http://halobates.de/blog/p/262
# https://sites.google.com/site/analysismethods/yasin-pubs
# https://download.01.org/perfmon/
# https://github.com/andikleen/pmu-tools/wiki/toplev-manual
#
# Helpers
print_error = lambda msg: False
smt_enabled = False
ebs_mode = False
version = "4.19-full-perf"
base_frequency = -1.0
Memory = 0
Average_Frequency = 0.0
def handle_error(obj, msg):
print_error(msg)
obj.errcount += 1
obj.val = 0
obj.thresh = False
def handle_error_metric(obj, msg):
print_error(msg)
obj.errcount += 1
obj.val = 0
# Constants
Mem_L2_Store_Cost = 11
Pipeline_Width = 4
Mem_STLB_Hit_Cost = 9
BAClear_Cost = 9
MS_Switches_Cost = 2
Avg_Assist_Cost = 100 * Pipeline_Width
OneMillion = 1000000
OneBillion = 1000000000
Energy_Unit = 61
Errata_Whitelist = "SKL/KBL091"
# Aux. formulas
def Backend_Bound_Cycles(self, EV, level):
return EV("CYCLE_ACTIVITY.STALLS_TOTAL", level) + Few_Uops_Executed_Threshold(self, EV, level) + EV("EXE_ACTIVITY.BOUND_ON_STORES", level)
def Br_DoI_Jumps(self, EV, level):
return EV("BR_INST_RETIRED.NEAR_TAKEN", level) - (EV("BR_INST_RETIRED.CONDITIONAL", level) - EV("BR_INST_RETIRED.NOT_TAKEN", level)) - 2 * EV("BR_INST_RETIRED.NEAR_CALL", level)
def Core_Bound_Cycles(self, EV, level):
return EV("CYCLE_ACTIVITY.STALLS_TOTAL", level) - EV("CYCLE_ACTIVITY.STALLS_MEM_ANY", level) + Few_Uops_Executed_Threshold(self, EV, level)
def Cycles_0_Ports_Utilized(self, EV, level):
return EV("UOPS_EXECUTED.CORE_CYCLES_NONE", level) / 2 if smt_enabled else EV("CYCLE_ACTIVITY.STALLS_TOTAL", level) - EV("CYCLE_ACTIVITY.STALLS_MEM_ANY", level)
def Cycles_1_Port_Utilized(self, EV, level):
return (EV("UOPS_EXECUTED.CORE_CYCLES_GE_1", level) - EV("UOPS_EXECUTED.CORE_CYCLES_GE_2", level)) / 2 if smt_enabled else EV("EXE_ACTIVITY.1_PORTS_UTIL", level)
def Cycles_2_Ports_Utilized(self, EV, level):
return (EV("UOPS_EXECUTED.CORE_CYCLES_GE_2", level) - EV("UOPS_EXECUTED.CORE_CYCLES_GE_3", level)) / 2 if smt_enabled else EV("EXE_ACTIVITY.2_PORTS_UTIL", level)
def Cycles_3m_Ports_Utilized(self, EV, level):
return EV("UOPS_EXECUTED.CORE_CYCLES_GE_3", level) / 2 if smt_enabled else EV("UOPS_EXECUTED.CORE_CYCLES_GE_3", level)
def DurationTimeInSeconds(self, EV, level):
return EV("interval-ms", 0) / 1000
def Execute_Cycles(self, EV, level):
return (EV("UOPS_EXECUTED.CORE_CYCLES_GE_1", level) / 2) if smt_enabled else EV("UOPS_EXECUTED.CORE_CYCLES_GE_1", level)
# factor used for metrics associating fixed costs for FB Hits - according to probability theory if all FB Hits come at a random rate in original L1_Miss cost interval then the average cost for each one is 0.5 of the fixed cost
def FBHit_Factor(self, EV, level):
return 1 + FBHit_per_L1Miss(self, EV, level) / 2
def FBHit_per_L1Miss(self, EV, level):
return EV("MEM_LOAD_RETIRED.FB_HIT", level) / LOAD_L1_MISS_NET(self, EV, level)
def Fetched_Uops(self, EV, level):
return EV("IDQ.DSB_UOPS", level) + EV("IDQ.MITE_UOPS", level) + EV("IDQ.MS_UOPS", level)
def Few_Uops_Executed_Threshold(self, EV, level):
return EV("EXE_ACTIVITY.1_PORTS_UTIL", level) + self.Retiring.compute(EV) * EV("EXE_ACTIVITY.2_PORTS_UTIL", level)
# Floating Point computational (arithmetic) Operations Count
def FLOP_Count(self, EV, level):
return (1 *(EV("FP_ARITH_INST_RETIRED.SCALAR_SINGLE", level) + EV("FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", level)) + 2 * EV("FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", level) + 4 *(EV("FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", level) + EV("FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", level)) + 8 *(EV("FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", level) + EV("FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", level)) + 16 * EV("FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", level))
# Floating Point computational (arithmetic) Operations Count
def FP_Arith_Scalar(self, EV, level):
return EV("FP_ARITH_INST_RETIRED.SCALAR_SINGLE", level) + EV("FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", level)
# Floating Point computational (arithmetic) Operations Count
def FP_Arith_Vector(self, EV, level):
return EV("FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", level) + EV("FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", level) + EV("FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", level) + EV("FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", level) + EV("FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", level) + EV("FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", level)
def HighIPC(self, EV, level):
return IPC(self, EV, level) / Pipeline_Width
def L2_Bound_Ratio(self, EV, level):
return (EV("CYCLE_ACTIVITY.STALLS_L1D_MISS", level) - EV("CYCLE_ACTIVITY.STALLS_L2_MISS", level)) / CLKS(self, EV, level)
def LOAD_L1_MISS_NET(self, EV, level):
return EV("MEM_LOAD_RETIRED.L1_MISS", level)
def LOAD_L2_HIT(self, EV, level):
return EV("MEM_LOAD_RETIRED.L2_HIT", level) * (1 + FBHit_per_L1Miss(self, EV, level))
def LOAD_L3_HIT(self, EV, level):
return EV("MEM_LOAD_RETIRED.L3_HIT", level)
def LOAD_XSNP_HIT(self, EV, level):
return EV("MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT", level) + EV("MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM", level) * (1 - True_XSNP_HitM_Fraction(self, EV, level))
def LOAD_XSNP_HITM(self, EV, level):
return EV("MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM", level) * True_XSNP_HitM_Fraction(self, EV, level)
def LOAD_XSNP_MISS(self, EV, level):
return EV("MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", level)
def MEM_Bound_Ratio(self, EV, level):
return EV("CYCLE_ACTIVITY.STALLS_L3_MISS", level) / CLKS(self, EV, level) + L2_Bound_Ratio(self, EV, level) - self.L2_Bound.compute(EV)
def Mem_Lock_St_Fraction(self, EV, level):
return EV("MEM_INST_RETIRED.LOCK_LOADS", level) / EV("MEM_INST_RETIRED.ALL_STORES", level)
def Memory_Bound_Fraction(self, EV, level):
return (EV("CYCLE_ACTIVITY.STALLS_MEM_ANY", level) + EV("EXE_ACTIVITY.BOUND_ON_STORES", level)) / Backend_Bound_Cycles(self, EV, level)
def Mispred_Clears_Fraction(self, EV, level):
return EV("BR_MISP_RETIRED.ALL_BRANCHES", level) / (EV("BR_MISP_RETIRED.ALL_BRANCHES", level) + EV("MACHINE_CLEARS.COUNT", level))
def OCR_all_rfo_l3_hit_snoop_hitm(self, EV, level):
return EV("OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE", level) + EV("OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE", level)
def OCR_all_rfo_l3_miss_remote_hitm(self, EV, level):
return EV("OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HITM", level) + EV("OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HITM", level)
def ORO_Demand_RFO_C1(self, EV, level):
return EV(lambda EV , level : min(EV("CPU_CLK_UNHALTED.THREAD", level) , EV("OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", level)) , level )
def ORO_DRD_Any_Cycles(self, EV, level):
return EV(lambda EV , level : min(EV("CPU_CLK_UNHALTED.THREAD", level) , EV("OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", level)) , level )
def ORO_DRD_BW_Cycles(self, EV, level):
return EV(lambda EV , level : min(EV("CPU_CLK_UNHALTED.THREAD", level) , EV("OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD:c4", level)) , level )
def Recovery_Cycles(self, EV, level):
return (EV("INT_MISC.RECOVERY_CYCLES_ANY", level) / 2) if smt_enabled else EV("INT_MISC.RECOVERY_CYCLES", level)
def Retire_Fraction(self, EV, level):
return Retired_Slots(self, EV, level) / EV("UOPS_ISSUED.ANY", level)
# Retired slots per Logical Processor
def Retired_Slots(self, EV, level):
return EV("UOPS_RETIRED.RETIRE_SLOTS", level)
def SQ_Full_Cycles(self, EV, level):
return (EV("OFFCORE_REQUESTS_BUFFER.SQ_FULL", level) / 2) if smt_enabled else EV("OFFCORE_REQUESTS_BUFFER.SQ_FULL", level)
def Store_L2_Hit_Cycles(self, EV, level):
return EV("L2_RQSTS.RFO_HIT", level) * Mem_L2_Store_Cost *(1 - Mem_Lock_St_Fraction(self, EV, level))
def True_XSNP_HitM_Fraction(self, EV, level):
return EV("OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE", level) / (EV("OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE", level) + EV("OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", level))
def Mem_XSNP_HitM_Cost(self, EV, level):
return 47.5 * Average_Frequency(self, EV, level)
def Mem_XSNP_Hit_Cost(self, EV, level):
return 47.5 * Average_Frequency(self, EV, level)
def Mem_XSNP_None_Cost(self, EV, level):
return 20.5 * Average_Frequency(self, EV, level)
def Mem_Local_DRAM_Cost(self, EV, level):
return 80 * Average_Frequency(self, EV, level)
def Mem_Remote_DRAM_Cost(self, EV, level):
return 147.5 * Average_Frequency(self, EV, level)
def Mem_Remote_HitM_Cost(self, EV, level):
return 110 * Average_Frequency(self, EV, level)
def Mem_Remote_Fwd_Cost(self, EV, level):
return 110 * Average_Frequency(self, EV, level)
def Mem_L2_Hit_Cost(self, EV, level):
return 3.5 * Average_Frequency(self, EV, level)
# Total pipeline cost of Branch Misprediction related bottlenecks
def Mispredictions(self, EV, level):
return 100 *(self.Branch_Mispredicts.compute(EV) + self.Fetch_Latency.compute(EV) * self.Mispredicts_Resteers.compute(EV) / (self.LCP.compute(EV) + self.ICache_Misses.compute(EV) + self.DSB_Switches.compute(EV) + self.Branch_Resteers.compute(EV) + self.MS_Switches.compute(EV) + self.ITLB_Misses.compute(EV)))
# Total pipeline cost of (external) Memory Bandwidth related bottlenecks
def Memory_Bandwidth(self, EV, level):
return 100 * self.Memory_Bound.compute(EV) * ((self.DRAM_Bound.compute(EV) / (self.L1_Bound.compute(EV) + self.L3_Bound.compute(EV) + self.DRAM_Bound.compute(EV) + self.Store_Bound.compute(EV) + self.L2_Bound.compute(EV))) * (self.MEM_Bandwidth.compute(EV) / (self.MEM_Latency.compute(EV) + self.MEM_Bandwidth.compute(EV))) + (self.L3_Bound.compute(EV) / (self.L1_Bound.compute(EV) + self.L3_Bound.compute(EV) + self.DRAM_Bound.compute(EV) + self.Store_Bound.compute(EV) + self.L2_Bound.compute(EV))) * (self.SQ_Full.compute(EV) / (self.L3_Hit_Latency.compute(EV) + self.Contested_Accesses.compute(EV) + self.SQ_Full.compute(EV) + self.Data_Sharing.compute(EV)))) + (self.L1_Bound.compute(EV) / (self.L1_Bound.compute(EV) + self.L3_Bound.compute(EV) + self.DRAM_Bound.compute(EV) + self.Store_Bound.compute(EV) + self.L2_Bound.compute(EV))) * (self.FB_Full.compute(EV) / (self.Store_Fwd_Blk.compute(EV) + self.DTLB_Load.compute(EV) + self.G4K_Aliasing.compute(EV) + self.Lock_Latency.compute(EV) + self.Split_Loads.compute(EV) + self.FB_Full.compute(EV)))
# Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches)
def Memory_Latency(self, EV, level):
return 100 * self.Memory_Bound.compute(EV) * ((self.DRAM_Bound.compute(EV) / (self.L1_Bound.compute(EV) + self.L3_Bound.compute(EV) + self.DRAM_Bound.compute(EV) + self.Store_Bound.compute(EV) + self.L2_Bound.compute(EV))) * (self.MEM_Latency.compute(EV) / (self.MEM_Latency.compute(EV) + self.MEM_Bandwidth.compute(EV))) + (self.L3_Bound.compute(EV) / (self.L1_Bound.compute(EV) + self.L3_Bound.compute(EV) + self.DRAM_Bound.compute(EV) + self.Store_Bound.compute(EV) + self.L2_Bound.compute(EV))) * (self.L3_Hit_Latency.compute(EV) / (self.L3_Hit_Latency.compute(EV) + self.Contested_Accesses.compute(EV) + self.SQ_Full.compute(EV) + self.Data_Sharing.compute(EV))) + (self.L2_Bound.compute(EV) / (self.L1_Bound.compute(EV) + self.L3_Bound.compute(EV) + self.DRAM_Bound.compute(EV) + self.Store_Bound.compute(EV) + self.L2_Bound.compute(EV))))
# Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches)
def Memory_Data_TLBs(self, EV, level):
return 100 * self.Memory_Bound.compute(EV) * ((self.L1_Bound.compute(EV) / (self.L1_Bound.compute(EV) + self.L3_Bound.compute(EV) + self.DRAM_Bound.compute(EV) + self.Store_Bound.compute(EV) + self.L2_Bound.compute(EV))) * (self.DTLB_Load.compute(EV) / (self.Store_Fwd_Blk.compute(EV) + self.DTLB_Load.compute(EV) + self.G4K_Aliasing.compute(EV) + self.Lock_Latency.compute(EV) + self.Split_Loads.compute(EV) + self.FB_Full.compute(EV))) + (self.Store_Bound.compute(EV) / (self.L1_Bound.compute(EV) + self.L3_Bound.compute(EV) + self.DRAM_Bound.compute(EV) + self.Store_Bound.compute(EV) + self.L2_Bound.compute(EV))) * (self.DTLB_Store.compute(EV) / (self.Split_Stores.compute(EV) + self.DTLB_Store.compute(EV) + self.Store_Latency.compute(EV) + self.False_Sharing.compute(EV))))
def Branching_Overhead(self, EV, level):
return 100 *(EV("BR_INST_RETIRED.CONDITIONAL", level) + 3 * EV("BR_INST_RETIRED.NEAR_CALL", level) + Br_DoI_Jumps(self, EV, level)) / SLOTS(self, EV, level)
def Big_Code(self, EV, level):
return 100 * self.Fetch_Latency.compute(EV) * (self.ITLB_Misses.compute(EV) + self.ICache_Misses.compute(EV) + self.Unknown_Branches.compute(EV)) / (self.LCP.compute(EV) + self.ICache_Misses.compute(EV) + self.DSB_Switches.compute(EV) + self.Branch_Resteers.compute(EV) + self.MS_Switches.compute(EV) + self.ITLB_Misses.compute(EV))
def Instruction_Fetch_BW(self, EV, level):
return 100 * self.Fetch_Bandwidth.compute(EV)
# Instructions Per Cycle (per Logical Processor)
def IPC(self, EV, level):
return EV("INST_RETIRED.ANY", level) / CLKS(self, EV, level)
# Uops Per Instruction
def UPI(self, EV, level):
return Retired_Slots(self, EV, level) / EV("INST_RETIRED.ANY", level)
# Instruction per taken branch
def IpTB(self, EV, level):
return EV("INST_RETIRED.ANY", level) / EV("BR_INST_RETIRED.NEAR_TAKEN", level)
# Cycles Per Instruction (per Logical Processor)
def CPI(self, EV, level):
return 1 / IPC(self, EV, level)
# Per-Logical Processor actual clocks when the Logical Processor is active.
def CLKS(self, EV, level):
return EV("CPU_CLK_UNHALTED.THREAD", level)
# Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)
def SLOTS(self, EV, level):
return Pipeline_Width * CORE_CLKS(self, EV, level)
# Instructions Per Cycle (per physical core)
def CoreIPC(self, EV, level):
return EV("INST_RETIRED.ANY", level) / CORE_CLKS(self, EV, level)
# Floating Point Operations Per Cycle
def FLOPc(self, EV, level):
return FLOP_Count(self, EV, level) / CORE_CLKS(self, EV, level)
# Actual per-core usage of the Floating Point execution units (regardless of the vector width).
def FP_Arith_Utilization(self, EV, level):
return (FP_Arith_Scalar(self, EV, level) + FP_Arith_Vector(self, EV, level)) / (2 * CORE_CLKS(self, EV, level))
# Instruction-Level-Parallelism (average number of uops executed when there is at least 1 uop executed)
def ILP(self, EV, level):
return EV("UOPS_EXECUTED.THREAD", level) / Execute_Cycles(self, EV, level)
# Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)
def Branch_Misprediction_Cost(self, EV, level):
return (self.Branch_Mispredicts.compute(EV) + self.Fetch_Latency.compute(EV) * self.Mispredicts_Resteers.compute(EV) / (self.LCP.compute(EV) + self.ICache_Misses.compute(EV) + self.DSB_Switches.compute(EV) + self.Branch_Resteers.compute(EV) + self.MS_Switches.compute(EV) + self.ITLB_Misses.compute(EV))) * SLOTS(self, EV, level) / EV("BR_MISP_RETIRED.ALL_BRANCHES", level)
# Number of Instructions per non-speculative Branch Misprediction (JEClear)
def IpMispredict(self, EV, level):
return EV("INST_RETIRED.ANY", level) / EV("BR_MISP_RETIRED.ALL_BRANCHES", level)
# Core actual clocks when any Logical Processor is active on the Physical Core
def CORE_CLKS(self, EV, level):
return ((EV("CPU_CLK_UNHALTED.THREAD", level) / 2) * (1 + EV("CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", level) / EV("CPU_CLK_UNHALTED.REF_XCLK", level))) if ebs_mode else(EV("CPU_CLK_UNHALTED.THREAD_ANY", level) / 2) if smt_enabled else CLKS(self, EV, level)
# Instructions per Load (lower number means higher occurrence rate)
def IpLoad(self, EV, level):
return EV("INST_RETIRED.ANY", level) / EV("MEM_INST_RETIRED.ALL_LOADS", level)
# Instructions per Store (lower number means higher occurrence rate)
def IpStore(self, EV, level):
return EV("INST_RETIRED.ANY", level) / EV("MEM_INST_RETIRED.ALL_STORES", level)
# Instructions per Branch (lower number means higher occurrence rate)
def IpBranch(self, EV, level):
return EV("INST_RETIRED.ANY", level) / EV("BR_INST_RETIRED.ALL_BRANCHES", level)
# Instructions per (near) call (lower number means higher occurrence rate)
def IpCall(self, EV, level):
return EV("INST_RETIRED.ANY", level) / EV("BR_INST_RETIRED.NEAR_CALL", level)
# Branch instructions per taken branch.
def BpTkBranch(self, EV, level):
return EV("BR_INST_RETIRED.ALL_BRANCHES", level) / EV("BR_INST_RETIRED.NEAR_TAKEN", level)
# Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)
def IpFLOP(self, EV, level):
return EV("INST_RETIRED.ANY", level) / FLOP_Count(self, EV, level)
# Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). Approximated prior to BDW.
def IpArith(self, EV, level):
return EV("INST_RETIRED.ANY", level) / (FP_Arith_Scalar(self, EV, level) + FP_Arith_Vector(self, EV, level))
# Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate)
def IpArith_Scalar_SP(self, EV, level):
return EV("INST_RETIRED.ANY", level) / EV("FP_ARITH_INST_RETIRED.SCALAR_SINGLE", level)
# Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate)
def IpArith_Scalar_DP(self, EV, level):
return EV("INST_RETIRED.ANY", level) / EV("FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", level)
# Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate)
def IpArith_AVX128(self, EV, level):
return EV("INST_RETIRED.ANY", level) / (EV("FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", level) + EV("FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", level))
# Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate)
def IpArith_AVX256(self, EV, level):
return EV("INST_RETIRED.ANY", level) / (EV("FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", level) + EV("FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", level))
# Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate)
def IpArith_AVX512(self, EV, level):
return EV("INST_RETIRED.ANY", level) / (EV("FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", level) + EV("FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", level))
# Total number of retired Instructions
def Instructions(self, EV, level):
return EV("INST_RETIRED.ANY", level)
# Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)
def DSB_Coverage(self, EV, level):
return EV("IDQ.DSB_UOPS", level) / Fetched_Uops(self, EV, level)
def Jump(self, EV, level):
return Br_DoI_Jumps(self, EV, level) / EV("BR_INST_RETIRED.ALL_BRANCHES", level)
# Actual Average Latency for L1 data-cache miss demand loads (in core cycles)
def Load_Miss_Real_Latency(self, EV, level):
return EV("L1D_PEND_MISS.PENDING", level) / (EV("MEM_LOAD_RETIRED.L1_MISS", level) + EV("MEM_LOAD_RETIRED.FB_HIT", level))
# Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)
def MLP(self, EV, level):
return EV("L1D_PEND_MISS.PENDING", level) / EV("L1D_PEND_MISS.PENDING_CYCLES", level)
# Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses
def Page_Walks_Utilization(self, EV, level):
return (EV("ITLB_MISSES.WALK_PENDING", level) + EV("DTLB_LOAD_MISSES.WALK_PENDING", level) + EV("DTLB_STORE_MISSES.WALK_PENDING", level) + EV("EPT.WALK_PENDING", level)) / (2 * CORE_CLKS(self, EV, level))
# Average data fill bandwidth to the L1 data cache [GB / sec]
def L1D_Cache_Fill_BW(self, EV, level):
return 64 * EV("L1D.REPLACEMENT", level) / OneBillion / Time(self, EV, level)
# Average data fill bandwidth to the L2 cache [GB / sec]
def L2_Cache_Fill_BW(self, EV, level):
return 64 * EV("L2_LINES_IN.ALL", level) / OneBillion / Time(self, EV, level)
# Average per-core data fill bandwidth to the L3 cache [GB / sec]
def L3_Cache_Fill_BW(self, EV, level):
return 64 * EV("LONGEST_LAT_CACHE.MISS", level) / OneBillion / Time(self, EV, level)
# Average per-core data access bandwidth to the L3 cache [GB / sec]
def L3_Cache_Access_BW(self, EV, level):
return 64 * EV("OFFCORE_REQUESTS.ALL_REQUESTS", level) / OneBillion / Time(self, EV, level)
# L1 cache true misses per kilo instruction for retired demand loads
def L1MPKI(self, EV, level):
return 1000 * EV("MEM_LOAD_RETIRED.L1_MISS", level) / EV("INST_RETIRED.ANY", level)
# L1 cache true misses per kilo instruction for all demand loads (including speculative)
def L1MPKI_Load(self, EV, level):
return 1000 * EV("L2_RQSTS.ALL_DEMAND_DATA_RD", level) / EV("INST_RETIRED.ANY", level)
# L2 cache true misses per kilo instruction for retired demand loads
def L2MPKI(self, EV, level):
return 1000 * EV("MEM_LOAD_RETIRED.L2_MISS", level) / EV("INST_RETIRED.ANY", level)
# L2 cache misses per kilo instruction for all request types (including speculative)
def L2MPKI_All(self, EV, level):
return 1000 * EV("L2_RQSTS.MISS", level) / EV("INST_RETIRED.ANY", level)
# L2 cache misses per kilo instruction for all demand loads (including speculative)
def L2MPKI_Load(self, EV, level):
return 1000 * EV("L2_RQSTS.DEMAND_DATA_RD_MISS", level) / EV("INST_RETIRED.ANY", level)
# L2 cache hits per kilo instruction for all request types (including speculative)
def L2HPKI_All(self, EV, level):
return 1000 *(EV("L2_RQSTS.REFERENCES", level) - EV("L2_RQSTS.MISS", level)) / EV("INST_RETIRED.ANY", level)
# L2 cache hits per kilo instruction for all demand loads (including speculative)
def L2HPKI_Load(self, EV, level):
return 1000 * EV("L2_RQSTS.DEMAND_DATA_RD_HIT", level) / EV("INST_RETIRED.ANY", level)
# L3 cache true misses per kilo instruction for retired demand loads
def L3MPKI(self, EV, level):
return 1000 * EV("MEM_LOAD_RETIRED.L3_MISS", level) / EV("INST_RETIRED.ANY", level)
# Fill Buffer (FB) true hits per kilo instructions for retired demand loads
def FB_HPKI(self, EV, level):
return 1000 * EV("MEM_LOAD_RETIRED.FB_HIT", level) / EV("INST_RETIRED.ANY", level)
# Rate of silent evictions from the L2 cache per Kilo instruction where the evicted lines are dropped (no writeback to L3 or memory)
def L2_Evictions_Silent_PKI(self, EV, level):
return 1000 * EV("L2_LINES_OUT.SILENT", level) / Instructions(self, EV, level)
# Rate of non silent evictions from the L2 cache per Kilo instruction
def L2_Evictions_NonSilent_PKI(self, EV, level):
return 1000 * EV("L2_LINES_OUT.NON_SILENT", level) / Instructions(self, EV, level)
# Average CPU Utilization
def CPU_Utilization(self, EV, level):
return EV("CPU_CLK_UNHALTED.REF_TSC", level) / EV("msr/tsc/", 0)
# Measured Average Frequency for unhalted processors [GHz]
def Average_Frequency(self, EV, level):
return Turbo_Utilization(self, EV, level) * EV("msr/tsc/", 0) / OneBillion / Time(self, EV, level)
# Giga Floating Point Operations Per Second
def GFLOPs(self, EV, level):
return (FLOP_Count(self, EV, level) / OneBillion) / Time(self, EV, level)
# Average Frequency Utilization relative nominal frequency
def Turbo_Utilization(self, EV, level):
return CLKS(self, EV, level) / EV("CPU_CLK_UNHALTED.REF_TSC", level)
# Fraction of Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.
def Power_License0_Utilization(self, EV, level):
return EV("CORE_POWER.LVL0_TURBO_LICENSE", level) / 2 / CORE_CLKS(self, EV, level) if smt_enabled else EV("CORE_POWER.LVL0_TURBO_LICENSE", level) / CORE_CLKS(self, EV, level)
# Fraction of Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.
def Power_License1_Utilization(self, EV, level):
return EV("CORE_POWER.LVL1_TURBO_LICENSE", level) / 2 / CORE_CLKS(self, EV, level) if smt_enabled else EV("CORE_POWER.LVL1_TURBO_LICENSE", level) / CORE_CLKS(self, EV, level)
# Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX). This includes high current AVX 512-bit instructions.
def Power_License2_Utilization(self, EV, level):
return EV("CORE_POWER.LVL2_TURBO_LICENSE", level) / 2 / CORE_CLKS(self, EV, level) if smt_enabled else EV("CORE_POWER.LVL2_TURBO_LICENSE", level) / CORE_CLKS(self, EV, level)
# Fraction of cycles where both hardware Logical Processors were active
def SMT_2T_Utilization(self, EV, level):
return 1 - EV("CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", level) / (EV("CPU_CLK_UNHALTED.REF_XCLK_ANY", level) / 2) if smt_enabled else 0
# Fraction of cycles spent in the Operating System (OS) Kernel mode
def Kernel_Utilization(self, EV, level):
return EV("CPU_CLK_UNHALTED.THREAD_P:SUP", level) / EV("CPU_CLK_UNHALTED.THREAD", level)
# Average external Memory Bandwidth Use for reads and writes [GB / sec]
def DRAM_BW_Use(self, EV, level):
return (64 *(EV("UNC_M_CAS_COUNT.RD", level) + EV("UNC_M_CAS_COUNT.WR", level)) / OneBillion) / Time(self, EV, level)
# Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches
def MEM_Read_Latency(self, EV, level):
return OneBillion *(EV("UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD", level) / EV("UNC_CHA_TOR_INSERTS.IA_MISS_DRD", level)) / (Socket_CLKS(self, EV, level) / Time(self, EV, level))
# Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches
def MEM_Parallel_Reads(self, EV, level):
return EV("UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD", level) / EV("UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD:c1", level)
# Average latency of data read request to external DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches
def MEM_DRAM_Read_Latency(self, EV, level):
return OneBillion *(EV("UNC_M_RPQ_OCCUPANCY", level) / EV("UNC_M_RPQ_INSERTS", level)) / EV("UNC_M_CLOCKTICKS:one_unit", level)
# Average IO (network or disk) Bandwidth Use for Writes [GB / sec]
def IO_Write_BW(self, EV, level):
return (EV("UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0", level) + EV("UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1", level) + EV("UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2", level) + EV("UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", level)) * 4 / OneBillion / Time(self, EV, level)
# Average IO (network or disk) Bandwidth Use for Reads [GB / sec]
def IO_Read_BW(self, EV, level):
return (EV("UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0", level) + EV("UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1", level) + EV("UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2", level) + EV("UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", level)) * 4 / OneBillion / Time(self, EV, level)
# Run duration time in seconds
def Time(self, EV, level):
return EV("interval-s", 0)
# Socket actual clocks when any core is active on that socket
def Socket_CLKS(self, EV, level):
return EV("UNC_CHA_CLOCKTICKS:one_unit", level)
# Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]
def IpFarBranch(self, EV, level):
return EV("INST_RETIRED.ANY", level) / EV("BR_INST_RETIRED.FAR_BRANCH:USER", level)
# Event groups
class Frontend_Bound:
name = "Frontend_Bound"
domain = "Slots"
area = "FE"
level = 1
htoff = False
sample = ['FRONTEND_RETIRED.LATENCY_GE_4:pp']
errcount = 0
sibling = None
server = False
metricgroup = ['TmaL1']
def compute(self, EV):
try:
self.val = EV("IDQ_UOPS_NOT_DELIVERED.CORE", 1) / SLOTS(self, EV, 1)
self.thresh = (self.val > 0.2)
except ZeroDivisionError:
handle_error(self, "Frontend_Bound zero division")
return self.val
desc = """
This category represents fraction of slots where the
processor's Frontend undersupplies its Backend. Frontend
denotes the first part of the processor core responsible to
fetch operations that are executed later on by the Backend
part. Within the Frontend; a branch predictor predicts the
next address to fetch; cache-lines are fetched from the
memory subsystem; parsed into instructions; and lastly
decoded into micro-operations (uops). Ideally the Frontend
can issue Machine_Width uops every cycle to the Backend.
Frontend Bound denotes unutilized issue-slots when there is
no Backend stall; i.e. bubbles where Frontend delivered no
uops while Backend could have accepted them. For example;
stalls due to instruction-cache misses would be categorized
under Frontend Bound."""
class Fetch_Latency:
name = "Fetch_Latency"
domain = "Slots"
area = "FE"
level = 2
htoff = False
sample = ['FRONTEND_RETIRED.LATENCY_GE_16:pp', 'FRONTEND_RETIRED.LATENCY_GE_8:pp']
errcount = 0
sibling = None
server = False
metricgroup = ['Frontend', 'TmaL2']
def compute(self, EV):
try:
self.val = Pipeline_Width * EV("IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", 2) / SLOTS(self, EV, 2)
self.thresh = (self.val > 0.15) & self.parent.thresh
except ZeroDivisionError:
handle_error(self, "Fetch_Latency zero division")
return self.val
desc = """
This metric represents fraction of slots the CPU was stalled
due to Frontend latency issues. For example; instruction-
cache misses; iTLB misses or fetch stalls after a branch
misprediction are categorized under Frontend Latency. In
such cases; the Frontend eventually delivers no uops for
some period."""
class ICache_Misses:
name = "ICache_Misses"
domain = "Clocks"
area = "FE"
level = 3
htoff = False
sample = ['FRONTEND_RETIRED.L2_MISS:pp', 'FRONTEND_RETIRED.L1I_MISS:pp']
errcount = 0
sibling = None
server = False
metricgroup = ['FetchLat', 'IcMiss']
def compute(self, EV):
try:
self.val = (EV("ICACHE_16B.IFDATA_STALL", 3) + 2 * EV("ICACHE_16B.IFDATA_STALL:c1:e1", 3)) / CLKS(self, EV, 3)
self.thresh = (self.val > 0.05) & self.parent.thresh
except ZeroDivisionError:
handle_error(self, "ICache_Misses zero division")
return self.val
desc = """
This metric represents fraction of cycles the CPU was
stalled due to instruction cache misses."""
class ITLB_Misses:
name = "ITLB_Misses"
domain = "Clocks"
area = "FE"
level = 3
htoff = False
sample = ['FRONTEND_RETIRED.STLB_MISS:pp', 'FRONTEND_RETIRED.ITLB_MISS:pp']
errcount = 0
sibling = None
server = False
metricgroup = ['FetchLat', 'MemoryTLB']
def compute(self, EV):
try:
self.val = EV("ICACHE_64B.IFTAG_STALL", 3) / CLKS(self, EV, 3)
self.thresh = (self.val > 0.05) & self.parent.thresh
except ZeroDivisionError:
handle_error(self, "ITLB_Misses zero division")
return self.val
desc = """
This metric represents fraction of cycles the CPU was
stalled due to Instruction TLB (ITLB) misses."""
class Branch_Resteers:
name = "Branch_Resteers"
domain = "Clocks_Estimated"
area = "FE"
level = 3
htoff = False
sample = ['BR_MISP_RETIRED.ALL_BRANCHES:pp']
errcount = 0
sibling = None
server = False
metricgroup = ['BadSpec', 'FetchLat']
def compute(self, EV):
try:
self.val = EV("INT_MISC.CLEAR_RESTEER_CYCLES", 3) / CLKS(self, EV, 3) + self.Unknown_Branches.compute(EV)
self.thresh = (self.val > 0.05) & self.parent.thresh
except ZeroDivisionError:
handle_error(self, "Branch_Resteers zero division")
return self.val
desc = """
This metric represents fraction of cycles the CPU was
stalled due to Branch Resteers. Branch Resteers estimates
the Frontend delay in fetching operations from corrected
path; following all sorts of miss-predicted branches. For
example; branchy code with lots of miss-predictions might
get categorized under Branch Resteers. Note the value of
this node may overlap with its siblings."""
class Mispredicts_Resteers:
name = "Mispredicts_Resteers"
domain = "Clocks"
area = "FE"
level = 4
htoff = False
sample = ['INT_MISC.CLEAR_RESTEER_CYCLES']
errcount = 0
sibling = None
server = False
metricgroup = ['BrMispredicts']
def compute(self, EV):
try:
self.val = Mispred_Clears_Fraction(self, EV, 4) * EV("INT_MISC.CLEAR_RESTEER_CYCLES", 4) / CLKS(self, EV, 4)
self.thresh = (self.val > 0.05) & self.parent.thresh
except ZeroDivisionError:
handle_error(self, "Mispredicts_Resteers zero division")
return self.val
desc = """
This metric represents fraction of cycles the CPU was
stalled due to Branch Resteers as a result of Branch
Misprediction at execution stage."""
class Clears_Resteers:
name = "Clears_Resteers"
domain = "Clocks"
area = "FE"
level = 4
htoff = False
sample = ['INT_MISC.CLEAR_RESTEER_CYCLES']
errcount = 0
sibling = None
server = False
metricgroup = ['MachineClears']
def compute(self, EV):
try:
self.val = (1 - Mispred_Clears_Fraction(self, EV, 4)) * EV("INT_MISC.CLEAR_RESTEER_CYCLES", 4) / CLKS(self, EV, 4)
self.thresh = (self.val > 0.05) & self.parent.thresh
except ZeroDivisionError:
handle_error(self, "Clears_Resteers zero division")
return self.val
desc = """
This metric represents fraction of cycles the CPU was
stalled due to Branch Resteers as a result of Machine
Clears."""
class Unknown_Branches:
name = "Unknown_Branches"
domain = "Clocks_Estimated"
area = "FE"
level = 4
htoff = False
sample = ['BACLEARS.ANY']
errcount = 0
sibling = None
server = False
metricgroup = ['FetchLat']
def compute(self, EV):
try:
self.val = BAClear_Cost * EV("BACLEARS.ANY", 4) / CLKS(self, EV, 4)
self.thresh = (self.val > 0.05) & self.parent.thresh
except ZeroDivisionError:
handle_error(self, "Unknown_Branches zero division")
return self.val
desc = """
This metric represents fraction of cycles the CPU was
stalled due to new branch address clears. These are fetched
branches the Branch Prediction Unit was unable to recognize
(First fetch or hitting BPU capacity limit)."""
class DSB_Switches:
name = "DSB_Switches"
domain = "Clocks"
area = "FE"
level = 3
htoff = False
sample = ['FRONTEND_RETIRED.DSB_MISS:pp']
errcount = 0
sibling = None
server = False
metricgroup = ['DSB', 'FetchLat']
def compute(self, EV):
try:
self.val = EV("DSB2MITE_SWITCHES.PENALTY_CYCLES", 3) / CLKS(self, EV, 3)
self.thresh = (self.val > 0.05) & self.parent.thresh
except ZeroDivisionError:
handle_error(self, "DSB_Switches zero division")
return self.val
desc = """
This metric represents fraction of cycles the CPU was
stalled due to switches from DSB to MITE pipelines. The DSB
(decoded i-cache; introduced with the Sandy Bridge
microarchitecture) pipeline has shorter latency and
delivered higher bandwidth than the MITE (legacy instruction
decode pipeline). Switching between the two pipelines can
cause penalties. This metric estimates when such penalty can
be exposed. Optimizing for better DSB hit rate may be
considered."""
class LCP:
name = "LCP"
domain = "Clocks"
area = "FE"
level = 3
htoff = False
sample = []
errcount = 0
sibling = None
server = False
metricgroup = ['FetchLat']
def compute(self, EV):
try:
self.val = EV("ILD_STALL.LCP", 3) / CLKS(self, EV, 3)
self.thresh = (self.val > 0.05) & self.parent.thresh
except ZeroDivisionError:
handle_error(self, "LCP zero division")
return self.val
desc = """
This metric represents fraction of cycles CPU was stalled
due to Length Changing Prefixes (LCPs). Using proper
compiler flags or Intel Compiler by default will certainly
avoid this."""
class MS_Switches:
name = "MS_Switches"
domain = "Clocks"
area = "FE"
level = 3
htoff = False
sample = ['IDQ.MS_SWITCHES']
errcount = 0
sibling = None
server = False
metricgroup = ['FetchLat', 'MicroSeq']
def compute(self, EV):
try:
self.val = MS_Switches_Cost * EV("IDQ.MS_SWITCHES", 3) / CLKS(self, EV, 3)
self.thresh = (self.val > 0.05) & self.parent.thresh
except ZeroDivisionError:
handle_error(self, "MS_Switches zero division")
return self.val
desc = """
This metric estimates the fraction of cycles when the CPU
was stalled due to switches of uop delivery to the Microcode
Sequencer (MS). Commonly used instructions are optimized for
delivery by the DSB (decoded i-cache) or MITE (legacy
instruction decode) pipelines. Certain operations cannot be
handled natively by the execution pipeline; and must be
performed by microcode (small programs injected into the
execution stream). Switching to the MS too often can
negatively impact performance. The MS is designated to
deliver long uop flows required by CISC instructions like
CPUID; or uncommon conditions like Floating Point Assists
when dealing with Denormals."""
class Fetch_Bandwidth:
name = "Fetch_Bandwidth"
domain = "Slots"
area = "FE"
level = 2
htoff = False
sample = ['FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1:pp', 'FRONTEND_RETIRED.LATENCY_GE_1:pp', 'FRONTEND_RETIRED.LATENCY_GE_2:pp']
errcount = 0
sibling = None
server = False
metricgroup = ['FetchBW', 'Frontend', 'TmaL2']
def compute(self, EV):
try:
self.val = self.Frontend_Bound.compute(EV) - self.Fetch_Latency.compute(EV)
self.thresh = (self.val > 0.1) & self.parent.thresh & (HighIPC(self, EV, 2) > 0)
except ZeroDivisionError:
handle_error(self, "Fetch_Bandwidth zero division")
return self.val
desc = """
This metric represents fraction of slots the CPU was stalled
due to Frontend bandwidth issues. For example;
inefficiencies at the instruction decoders; or code
restrictions for caching in the DSB (decoded uops cache) are
categorized under Frontend Bandwidth. In such cases; the
Frontend typically delivers non-optimal amount of uops to
the Backend (less than four)."""
class MITE:
name = "MITE"
domain = "Slots_Estimated"
area = "FE"
level = 3
htoff = False
sample = ['FRONTEND_RETIRED.DSB_MISS:pp']
errcount = 0
sibling = None
server = False
metricgroup = ['FetchBW']
def compute(self, EV):
try:
self.val = (EV("IDQ.ALL_MITE_CYCLES_ANY_UOPS", 3) - EV("IDQ.ALL_MITE_CYCLES_4_UOPS", 3)) / CORE_CLKS(self, EV, 3) / 2
self.thresh = (self.val > 0.15) & self.parent.thresh
except ZeroDivisionError:
handle_error(self, "MITE zero division")
return self.val
desc = """
This metric represents Core fraction of cycles in which CPU
was likely limited due to the MITE pipeline (Legacy Decode
Pipeline). This pipeline is used for code that was not pre-
cached in the DSB or LSD. For example; inefficiencies in the
instruction decoders are categorized here."""
class DSB:
name = "DSB"
domain = "Slots_Estimated"
area = "FE"
level = 3
htoff = False
sample = []
errcount = 0
sibling = None
server = False
metricgroup = ['DSB', 'FetchBW']
def compute(self, EV):
try:
self.val = (EV("IDQ.ALL_DSB_CYCLES_ANY_UOPS", 3) - EV("IDQ.ALL_DSB_CYCLES_4_UOPS", 3)) / CORE_CLKS(self, EV, 3) / 2
self.thresh = (self.val > 0.15) & self.parent.thresh
except ZeroDivisionError:
handle_error(self, "DSB zero division")
return self.val
desc = """
This metric represents Core fraction of cycles in which CPU
was likely limited due to DSB (decoded uop cache) fetch
pipeline. For example; inefficient utilization of the DSB
cache structure or bank conflict when reading from it; are
categorized here."""
class Bad_Speculation:
name = "Bad_Speculation"
domain = "Slots"
area = "BAD"
level = 1
htoff = False
sample = []
errcount = 0
sibling = None
server = False
metricgroup = ['BadSpec', 'TmaL1']
def compute(self, EV):
try:
self.val = (EV("UOPS_ISSUED.ANY", 1) - Retired_Slots(self, EV, 1) + Pipeline_Width * Recovery_Cycles(self, EV, 1)) / SLOTS(self, EV, 1)
self.thresh = (self.val > 0.15)
except ZeroDivisionError:
handle_error(self, "Bad_Speculation zero division")
return self.val
desc = """
This category represents fraction of slots wasted due to
incorrect speculations. This include slots used to issue
uops that do not eventually get retired and slots for which
the issue-pipeline was blocked due to recovery from earlier
incorrect speculation. For example; wasted work due to miss-
predicted branches are categorized under Bad Speculation
category. Incorrect data speculation followed by Memory
Ordering Nukes is another example."""
class Branch_Mispredicts:
name = "Branch_Mispredicts"
domain = "Slots"
area = "BAD"
level = 2
htoff = False
sample = ['BR_MISP_RETIRED.ALL_BRANCHES:pp']
errcount = 0
sibling = None
server = False
metricgroup = ['BadSpec', 'BrMispredicts', 'TmaL2']
def compute(self, EV):
try:
self.val = Mispred_Clears_Fraction(self, EV, 2) * self.Bad_Speculation.compute(EV)
self.thresh = (self.val > 0.05) & self.parent.thresh
except ZeroDivisionError:
handle_error(self, "Branch_Mispredicts zero division")
return self.val
desc = """
This metric represents fraction of slots the CPU has wasted
due to Branch Misprediction. These slots are either wasted
by uops fetched from an incorrectly speculated program path;
or stalls when the out-of-order part of the machine needs to
recover its state from a speculative path."""
class Machine_Clears:
name = "Machine_Clears"
domain = "Slots"
area = "BAD"
level = 2
htoff = False
sample = ['MACHINE_CLEARS.COUNT']
errcount = 0
sibling = None
server = False
metricgroup = ['BadSpec', 'MachineClears', 'TmaL2']
def compute(self, EV):
try:
self.val = self.Bad_Speculation.compute(EV) - self.Branch_Mispredicts.compute(EV)
self.thresh = (self.val > 0.05) & self.parent.thresh
except ZeroDivisionError:
handle_error(self, "Machine_Clears zero division")
return self.val
desc = """
This metric represents fraction of slots the CPU has wasted
due to Machine Clears. These slots are either wasted by
uops fetched prior to the clear; or stalls the out-of-order
portion of the machine needs to recover its state after the
clear. For example; this can happen due to memory ordering
Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code
(SMC) nukes."""
class Backend_Bound:
name = "Backend_Bound"
domain = "Slots"
area = "BE"
level = 1
htoff = False
sample = []
errcount = 0
sibling = None
server = False
metricgroup = ['TmaL1']
def compute(self, EV):
try:
self.val = 1 - self.Frontend_Bound.compute(EV) - (EV("UOPS_ISSUED.ANY", 1) + Pipeline_Width * Recovery_Cycles(self, EV, 1)) / SLOTS(self, EV, 1)
self.thresh = (self.val > 0.2)
except ZeroDivisionError:
handle_error(self, "Backend_Bound zero division")
return self.val
desc = """
This category represents fraction of slots where no uops are
being delivered due to a lack of required resources for
accepting new uops in the Backend. Backend is the portion of
the processor core where the out-of-order scheduler
dispatches ready uops into their respective execution units;
and once completed these uops get retired according to
program order. For example; stalls due to data-cache misses
or stalls due to the divider unit being overloaded are both
categorized under Backend Bound. Backend Bound is further
divided into two main categories: Memory Bound and Core
Bound."""
class Memory_Bound:
name = "Memory_Bound"
domain = "Slots"
area = "BE/Mem"
level = 2
htoff = False
sample = []
errcount = 0
sibling = None
server = False
metricgroup = ['Backend', 'TmaL2']
def compute(self, EV):
try:
self.val = Memory_Bound_Fraction(self, EV, 2) * self.Backend_Bound.compute(EV)
self.thresh = (self.val > 0.2) & self.parent.thresh
except ZeroDivisionError:
handle_error(self, "Memory_Bound zero division")
return self.val
desc = """
This metric represents fraction of slots the Memory
subsystem within the Backend was a bottleneck. Memory Bound
estimates fraction of slots where pipeline is likely stalled
due to demand load or store instructions. This accounts
mainly for (1) non-completed in-flight memory demand loads
which coincides with execution units starvation; in addition
to (2) cases where stores could impose backpressure on the