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translate.c
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translate.c
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/*
* S/390 translation
*
* Copyright (c) 2009 Ulrich Hecht
* Copyright (c) 2010 Alexander Graf
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
/* #define DEBUG_ILLEGAL_INSTRUCTIONS */
/* #define DEBUG_INLINE_BRANCHES */
#define S390X_DEBUG_DISAS
/* #define S390X_DEBUG_DISAS_VERBOSE */
#ifdef S390X_DEBUG_DISAS_VERBOSE
# define LOG_DISAS(...) qemu_log(__VA_ARGS__)
#else
# define LOG_DISAS(...) do { } while (0)
#endif
#include "cpu.h"
#include "disas.h"
#include "tcg-op.h"
#include "qemu-log.h"
/* global register indexes */
static TCGv_ptr cpu_env;
#include "gen-icount.h"
#include "helper.h"
#define GEN_HELPER 1
#include "helper.h"
typedef struct DisasContext DisasContext;
struct DisasContext {
uint64_t pc;
int is_jmp;
enum cc_op cc_op;
struct TranslationBlock *tb;
};
#define DISAS_EXCP 4
static void gen_op_calc_cc(DisasContext *s);
#ifdef DEBUG_INLINE_BRANCHES
static uint64_t inline_branch_hit[CC_OP_MAX];
static uint64_t inline_branch_miss[CC_OP_MAX];
#endif
static inline void debug_insn(uint64_t insn)
{
LOG_DISAS("insn: 0x%" PRIx64 "\n", insn);
}
static inline uint64_t pc_to_link_info(DisasContext *s, uint64_t pc)
{
if (!(s->tb->flags & FLAG_MASK_64)) {
if (s->tb->flags & FLAG_MASK_32) {
return pc | 0x80000000;
}
}
return pc;
}
void cpu_dump_state(CPUS390XState *env, FILE *f, fprintf_function cpu_fprintf,
int flags)
{
int i;
for (i = 0; i < 16; i++) {
cpu_fprintf(f, "R%02d=%016" PRIx64, i, env->regs[i]);
if ((i % 4) == 3) {
cpu_fprintf(f, "\n");
} else {
cpu_fprintf(f, " ");
}
}
for (i = 0; i < 16; i++) {
cpu_fprintf(f, "F%02d=%016" PRIx64, i, *(uint64_t *)&env->fregs[i]);
if ((i % 4) == 3) {
cpu_fprintf(f, "\n");
} else {
cpu_fprintf(f, " ");
}
}
cpu_fprintf(f, "\n");
#ifndef CONFIG_USER_ONLY
for (i = 0; i < 16; i++) {
cpu_fprintf(f, "C%02d=%016" PRIx64, i, env->cregs[i]);
if ((i % 4) == 3) {
cpu_fprintf(f, "\n");
} else {
cpu_fprintf(f, " ");
}
}
#endif
cpu_fprintf(f, "\n");
if (env->cc_op > 3) {
cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %15s\n",
env->psw.mask, env->psw.addr, cc_name(env->cc_op));
} else {
cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %02x\n",
env->psw.mask, env->psw.addr, env->cc_op);
}
#ifdef DEBUG_INLINE_BRANCHES
for (i = 0; i < CC_OP_MAX; i++) {
cpu_fprintf(f, " %15s = %10ld\t%10ld\n", cc_name(i),
inline_branch_miss[i], inline_branch_hit[i]);
}
#endif
}
static TCGv_i64 psw_addr;
static TCGv_i64 psw_mask;
static TCGv_i32 cc_op;
static TCGv_i64 cc_src;
static TCGv_i64 cc_dst;
static TCGv_i64 cc_vr;
static char cpu_reg_names[10*3 + 6*4];
static TCGv_i64 regs[16];
static uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
void s390x_translate_init(void)
{
int i;
size_t cpu_reg_names_size = sizeof(cpu_reg_names);
char *p;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
psw_addr = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUS390XState, psw.addr),
"psw_addr");
psw_mask = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUS390XState, psw.mask),
"psw_mask");
cc_op = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUS390XState, cc_op),
"cc_op");
cc_src = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUS390XState, cc_src),
"cc_src");
cc_dst = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUS390XState, cc_dst),
"cc_dst");
cc_vr = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUS390XState, cc_vr),
"cc_vr");
p = cpu_reg_names;
for (i = 0; i < 16; i++) {
snprintf(p, cpu_reg_names_size, "r%d", i);
regs[i] = tcg_global_mem_new(TCG_AREG0,
offsetof(CPUS390XState, regs[i]), p);
p += (i < 10) ? 3 : 4;
cpu_reg_names_size -= (i < 10) ? 3 : 4;
}
}
static inline TCGv_i64 load_reg(int reg)
{
TCGv_i64 r = tcg_temp_new_i64();
tcg_gen_mov_i64(r, regs[reg]);
return r;
}
static inline TCGv_i64 load_freg(int reg)
{
TCGv_i64 r = tcg_temp_new_i64();
tcg_gen_ld_i64(r, cpu_env, offsetof(CPUS390XState, fregs[reg].d));
return r;
}
static inline TCGv_i32 load_freg32(int reg)
{
TCGv_i32 r = tcg_temp_new_i32();
tcg_gen_ld_i32(r, cpu_env, offsetof(CPUS390XState, fregs[reg].l.upper));
return r;
}
static inline TCGv_i32 load_reg32(int reg)
{
TCGv_i32 r = tcg_temp_new_i32();
tcg_gen_trunc_i64_i32(r, regs[reg]);
return r;
}
static inline TCGv_i64 load_reg32_i64(int reg)
{
TCGv_i64 r = tcg_temp_new_i64();
tcg_gen_ext32s_i64(r, regs[reg]);
return r;
}
static inline void store_reg(int reg, TCGv_i64 v)
{
tcg_gen_mov_i64(regs[reg], v);
}
static inline void store_freg(int reg, TCGv_i64 v)
{
tcg_gen_st_i64(v, cpu_env, offsetof(CPUS390XState, fregs[reg].d));
}
static inline void store_reg32(int reg, TCGv_i32 v)
{
#if HOST_LONG_BITS == 32
tcg_gen_mov_i32(TCGV_LOW(regs[reg]), v);
#else
TCGv_i64 tmp = tcg_temp_new_i64();
tcg_gen_extu_i32_i64(tmp, v);
/* 32 bit register writes keep the upper half */
tcg_gen_deposit_i64(regs[reg], regs[reg], tmp, 0, 32);
tcg_temp_free_i64(tmp);
#endif
}
static inline void store_reg32_i64(int reg, TCGv_i64 v)
{
/* 32 bit register writes keep the upper half */
#if HOST_LONG_BITS == 32
tcg_gen_mov_i32(TCGV_LOW(regs[reg]), TCGV_LOW(v));
#else
tcg_gen_deposit_i64(regs[reg], regs[reg], v, 0, 32);
#endif
}
static inline void store_reg16(int reg, TCGv_i32 v)
{
TCGv_i64 tmp = tcg_temp_new_i64();
tcg_gen_extu_i32_i64(tmp, v);
/* 16 bit register writes keep the upper bytes */
tcg_gen_deposit_i64(regs[reg], regs[reg], tmp, 0, 16);
tcg_temp_free_i64(tmp);
}
static inline void store_reg8(int reg, TCGv_i64 v)
{
/* 8 bit register writes keep the upper bytes */
tcg_gen_deposit_i64(regs[reg], regs[reg], v, 0, 8);
}
static inline void store_freg32(int reg, TCGv_i32 v)
{
tcg_gen_st_i32(v, cpu_env, offsetof(CPUS390XState, fregs[reg].l.upper));
}
static inline void update_psw_addr(DisasContext *s)
{
/* psw.addr */
tcg_gen_movi_i64(psw_addr, s->pc);
}
static inline void potential_page_fault(DisasContext *s)
{
#ifndef CONFIG_USER_ONLY
update_psw_addr(s);
gen_op_calc_cc(s);
#endif
}
static inline uint64_t ld_code2(uint64_t pc)
{
return (uint64_t)lduw_code(pc);
}
static inline uint64_t ld_code4(uint64_t pc)
{
return (uint64_t)ldl_code(pc);
}
static inline uint64_t ld_code6(uint64_t pc)
{
uint64_t opc;
opc = (uint64_t)lduw_code(pc) << 32;
opc |= (uint64_t)(uint32_t)ldl_code(pc+2);
return opc;
}
static inline int get_mem_index(DisasContext *s)
{
switch (s->tb->flags & FLAG_MASK_ASC) {
case PSW_ASC_PRIMARY >> 32:
return 0;
case PSW_ASC_SECONDARY >> 32:
return 1;
case PSW_ASC_HOME >> 32:
return 2;
default:
tcg_abort();
break;
}
}
static inline void gen_debug(DisasContext *s)
{
TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG);
update_psw_addr(s);
gen_op_calc_cc(s);
gen_helper_exception(tmp);
tcg_temp_free_i32(tmp);
s->is_jmp = DISAS_EXCP;
}
#ifdef CONFIG_USER_ONLY
static void gen_illegal_opcode(DisasContext *s, int ilc)
{
TCGv_i32 tmp = tcg_const_i32(EXCP_SPEC);
update_psw_addr(s);
gen_op_calc_cc(s);
gen_helper_exception(tmp);
tcg_temp_free_i32(tmp);
s->is_jmp = DISAS_EXCP;
}
#else /* CONFIG_USER_ONLY */
static void debug_print_inst(DisasContext *s, int ilc)
{
#ifdef DEBUG_ILLEGAL_INSTRUCTIONS
uint64_t inst = 0;
switch (ilc & 3) {
case 1:
inst = ld_code2(s->pc);
break;
case 2:
inst = ld_code4(s->pc);
break;
case 3:
inst = ld_code6(s->pc);
break;
}
fprintf(stderr, "Illegal instruction [%d at %016" PRIx64 "]: 0x%016"
PRIx64 "\n", ilc, s->pc, inst);
#endif
}
static void gen_program_exception(DisasContext *s, int ilc, int code)
{
TCGv_i32 tmp;
debug_print_inst(s, ilc);
/* remember what pgm exeption this was */
tmp = tcg_const_i32(code);
tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUS390XState, int_pgm_code));
tcg_temp_free_i32(tmp);
tmp = tcg_const_i32(ilc);
tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUS390XState, int_pgm_ilc));
tcg_temp_free_i32(tmp);
/* advance past instruction */
s->pc += (ilc * 2);
update_psw_addr(s);
/* save off cc */
gen_op_calc_cc(s);
/* trigger exception */
tmp = tcg_const_i32(EXCP_PGM);
gen_helper_exception(tmp);
tcg_temp_free_i32(tmp);
/* end TB here */
s->is_jmp = DISAS_EXCP;
}
static void gen_illegal_opcode(DisasContext *s, int ilc)
{
gen_program_exception(s, ilc, PGM_SPECIFICATION);
}
static void gen_privileged_exception(DisasContext *s, int ilc)
{
gen_program_exception(s, ilc, PGM_PRIVILEGED);
}
static void check_privileged(DisasContext *s, int ilc)
{
if (s->tb->flags & (PSW_MASK_PSTATE >> 32)) {
gen_privileged_exception(s, ilc);
}
}
#endif /* CONFIG_USER_ONLY */
static TCGv_i64 get_address(DisasContext *s, int x2, int b2, int d2)
{
TCGv_i64 tmp;
/* 31-bitify the immediate part; register contents are dealt with below */
if (!(s->tb->flags & FLAG_MASK_64)) {
d2 &= 0x7fffffffUL;
}
if (x2) {
if (d2) {
tmp = tcg_const_i64(d2);
tcg_gen_add_i64(tmp, tmp, regs[x2]);
} else {
tmp = load_reg(x2);
}
if (b2) {
tcg_gen_add_i64(tmp, tmp, regs[b2]);
}
} else if (b2) {
if (d2) {
tmp = tcg_const_i64(d2);
tcg_gen_add_i64(tmp, tmp, regs[b2]);
} else {
tmp = load_reg(b2);
}
} else {
tmp = tcg_const_i64(d2);
}
/* 31-bit mode mask if there are values loaded from registers */
if (!(s->tb->flags & FLAG_MASK_64) && (x2 || b2)) {
tcg_gen_andi_i64(tmp, tmp, 0x7fffffffUL);
}
return tmp;
}
static void gen_op_movi_cc(DisasContext *s, uint32_t val)
{
s->cc_op = CC_OP_CONST0 + val;
}
static void gen_op_update1_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 dst)
{
tcg_gen_discard_i64(cc_src);
tcg_gen_mov_i64(cc_dst, dst);
tcg_gen_discard_i64(cc_vr);
s->cc_op = op;
}
static void gen_op_update1_cc_i32(DisasContext *s, enum cc_op op, TCGv_i32 dst)
{
tcg_gen_discard_i64(cc_src);
tcg_gen_extu_i32_i64(cc_dst, dst);
tcg_gen_discard_i64(cc_vr);
s->cc_op = op;
}
static void gen_op_update2_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 src,
TCGv_i64 dst)
{
tcg_gen_mov_i64(cc_src, src);
tcg_gen_mov_i64(cc_dst, dst);
tcg_gen_discard_i64(cc_vr);
s->cc_op = op;
}
static void gen_op_update2_cc_i32(DisasContext *s, enum cc_op op, TCGv_i32 src,
TCGv_i32 dst)
{
tcg_gen_extu_i32_i64(cc_src, src);
tcg_gen_extu_i32_i64(cc_dst, dst);
tcg_gen_discard_i64(cc_vr);
s->cc_op = op;
}
static void gen_op_update3_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 src,
TCGv_i64 dst, TCGv_i64 vr)
{
tcg_gen_mov_i64(cc_src, src);
tcg_gen_mov_i64(cc_dst, dst);
tcg_gen_mov_i64(cc_vr, vr);
s->cc_op = op;
}
static void gen_op_update3_cc_i32(DisasContext *s, enum cc_op op, TCGv_i32 src,
TCGv_i32 dst, TCGv_i32 vr)
{
tcg_gen_extu_i32_i64(cc_src, src);
tcg_gen_extu_i32_i64(cc_dst, dst);
tcg_gen_extu_i32_i64(cc_vr, vr);
s->cc_op = op;
}
static inline void set_cc_nz_u32(DisasContext *s, TCGv_i32 val)
{
gen_op_update1_cc_i32(s, CC_OP_NZ, val);
}
static inline void set_cc_nz_u64(DisasContext *s, TCGv_i64 val)
{
gen_op_update1_cc_i64(s, CC_OP_NZ, val);
}
static inline void cmp_32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2,
enum cc_op cond)
{
gen_op_update2_cc_i32(s, cond, v1, v2);
}
static inline void cmp_64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2,
enum cc_op cond)
{
gen_op_update2_cc_i64(s, cond, v1, v2);
}
static inline void cmp_s32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2)
{
cmp_32(s, v1, v2, CC_OP_LTGT_32);
}
static inline void cmp_u32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2)
{
cmp_32(s, v1, v2, CC_OP_LTUGTU_32);
}
static inline void cmp_s32c(DisasContext *s, TCGv_i32 v1, int32_t v2)
{
/* XXX optimize for the constant? put it in s? */
TCGv_i32 tmp = tcg_const_i32(v2);
cmp_32(s, v1, tmp, CC_OP_LTGT_32);
tcg_temp_free_i32(tmp);
}
static inline void cmp_u32c(DisasContext *s, TCGv_i32 v1, uint32_t v2)
{
TCGv_i32 tmp = tcg_const_i32(v2);
cmp_32(s, v1, tmp, CC_OP_LTUGTU_32);
tcg_temp_free_i32(tmp);
}
static inline void cmp_s64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2)
{
cmp_64(s, v1, v2, CC_OP_LTGT_64);
}
static inline void cmp_u64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2)
{
cmp_64(s, v1, v2, CC_OP_LTUGTU_64);
}
static inline void cmp_s64c(DisasContext *s, TCGv_i64 v1, int64_t v2)
{
TCGv_i64 tmp = tcg_const_i64(v2);
cmp_s64(s, v1, tmp);
tcg_temp_free_i64(tmp);
}
static inline void cmp_u64c(DisasContext *s, TCGv_i64 v1, uint64_t v2)
{
TCGv_i64 tmp = tcg_const_i64(v2);
cmp_u64(s, v1, tmp);
tcg_temp_free_i64(tmp);
}
static inline void set_cc_s32(DisasContext *s, TCGv_i32 val)
{
gen_op_update1_cc_i32(s, CC_OP_LTGT0_32, val);
}
static inline void set_cc_s64(DisasContext *s, TCGv_i64 val)
{
gen_op_update1_cc_i64(s, CC_OP_LTGT0_64, val);
}
static void set_cc_add64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2, TCGv_i64 vr)
{
gen_op_update3_cc_i64(s, CC_OP_ADD_64, v1, v2, vr);
}
static void set_cc_addu64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2,
TCGv_i64 vr)
{
gen_op_update3_cc_i64(s, CC_OP_ADDU_64, v1, v2, vr);
}
static void set_cc_sub64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2, TCGv_i64 vr)
{
gen_op_update3_cc_i64(s, CC_OP_SUB_64, v1, v2, vr);
}
static void set_cc_subu64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2,
TCGv_i64 vr)
{
gen_op_update3_cc_i64(s, CC_OP_SUBU_64, v1, v2, vr);
}
static void set_cc_abs64(DisasContext *s, TCGv_i64 v1)
{
gen_op_update1_cc_i64(s, CC_OP_ABS_64, v1);
}
static void set_cc_nabs64(DisasContext *s, TCGv_i64 v1)
{
gen_op_update1_cc_i64(s, CC_OP_NABS_64, v1);
}
static void set_cc_add32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2, TCGv_i32 vr)
{
gen_op_update3_cc_i32(s, CC_OP_ADD_32, v1, v2, vr);
}
static void set_cc_addu32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2,
TCGv_i32 vr)
{
gen_op_update3_cc_i32(s, CC_OP_ADDU_32, v1, v2, vr);
}
static void set_cc_sub32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2, TCGv_i32 vr)
{
gen_op_update3_cc_i32(s, CC_OP_SUB_32, v1, v2, vr);
}
static void set_cc_subu32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2,
TCGv_i32 vr)
{
gen_op_update3_cc_i32(s, CC_OP_SUBU_32, v1, v2, vr);
}
static void set_cc_abs32(DisasContext *s, TCGv_i32 v1)
{
gen_op_update1_cc_i32(s, CC_OP_ABS_32, v1);
}
static void set_cc_nabs32(DisasContext *s, TCGv_i32 v1)
{
gen_op_update1_cc_i32(s, CC_OP_NABS_32, v1);
}
static void set_cc_comp32(DisasContext *s, TCGv_i32 v1)
{
gen_op_update1_cc_i32(s, CC_OP_COMP_32, v1);
}
static void set_cc_comp64(DisasContext *s, TCGv_i64 v1)
{
gen_op_update1_cc_i64(s, CC_OP_COMP_64, v1);
}
static void set_cc_icm(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2)
{
gen_op_update2_cc_i32(s, CC_OP_ICM, v1, v2);
}
static void set_cc_cmp_f32_i64(DisasContext *s, TCGv_i32 v1, TCGv_i64 v2)
{
tcg_gen_extu_i32_i64(cc_src, v1);
tcg_gen_mov_i64(cc_dst, v2);
tcg_gen_discard_i64(cc_vr);
s->cc_op = CC_OP_LTGT_F32;
}
static void set_cc_nz_f32(DisasContext *s, TCGv_i32 v1)
{
gen_op_update1_cc_i32(s, CC_OP_NZ_F32, v1);
}
static inline void set_cc_nz_f64(DisasContext *s, TCGv_i64 v1)
{
gen_op_update1_cc_i64(s, CC_OP_NZ_F64, v1);
}
/* CC value is in env->cc_op */
static inline void set_cc_static(DisasContext *s)
{
tcg_gen_discard_i64(cc_src);
tcg_gen_discard_i64(cc_dst);
tcg_gen_discard_i64(cc_vr);
s->cc_op = CC_OP_STATIC;
}
static inline void gen_op_set_cc_op(DisasContext *s)
{
if (s->cc_op != CC_OP_DYNAMIC && s->cc_op != CC_OP_STATIC) {
tcg_gen_movi_i32(cc_op, s->cc_op);
}
}
static inline void gen_update_cc_op(DisasContext *s)
{
gen_op_set_cc_op(s);
}
/* calculates cc into cc_op */
static void gen_op_calc_cc(DisasContext *s)
{
TCGv_i32 local_cc_op = tcg_const_i32(s->cc_op);
TCGv_i64 dummy = tcg_const_i64(0);
switch (s->cc_op) {
case CC_OP_CONST0:
case CC_OP_CONST1:
case CC_OP_CONST2:
case CC_OP_CONST3:
/* s->cc_op is the cc value */
tcg_gen_movi_i32(cc_op, s->cc_op - CC_OP_CONST0);
break;
case CC_OP_STATIC:
/* env->cc_op already is the cc value */
break;
case CC_OP_NZ:
case CC_OP_ABS_64:
case CC_OP_NABS_64:
case CC_OP_ABS_32:
case CC_OP_NABS_32:
case CC_OP_LTGT0_32:
case CC_OP_LTGT0_64:
case CC_OP_COMP_32:
case CC_OP_COMP_64:
case CC_OP_NZ_F32:
case CC_OP_NZ_F64:
/* 1 argument */
gen_helper_calc_cc(cc_op, local_cc_op, dummy, cc_dst, dummy);
break;
case CC_OP_ICM:
case CC_OP_LTGT_32:
case CC_OP_LTGT_64:
case CC_OP_LTUGTU_32:
case CC_OP_LTUGTU_64:
case CC_OP_TM_32:
case CC_OP_TM_64:
case CC_OP_LTGT_F32:
case CC_OP_LTGT_F64:
case CC_OP_SLAG:
/* 2 arguments */
gen_helper_calc_cc(cc_op, local_cc_op, cc_src, cc_dst, dummy);
break;
case CC_OP_ADD_64:
case CC_OP_ADDU_64:
case CC_OP_SUB_64:
case CC_OP_SUBU_64:
case CC_OP_ADD_32:
case CC_OP_ADDU_32:
case CC_OP_SUB_32:
case CC_OP_SUBU_32:
/* 3 arguments */
gen_helper_calc_cc(cc_op, local_cc_op, cc_src, cc_dst, cc_vr);
break;
case CC_OP_DYNAMIC:
/* unknown operation - assume 3 arguments and cc_op in env */
gen_helper_calc_cc(cc_op, cc_op, cc_src, cc_dst, cc_vr);
break;
default:
tcg_abort();
}
tcg_temp_free_i32(local_cc_op);
/* We now have cc in cc_op as constant */
set_cc_static(s);
}
static inline void decode_rr(DisasContext *s, uint64_t insn, int *r1, int *r2)
{
debug_insn(insn);
*r1 = (insn >> 4) & 0xf;
*r2 = insn & 0xf;
}
static inline TCGv_i64 decode_rx(DisasContext *s, uint64_t insn, int *r1,
int *x2, int *b2, int *d2)
{
debug_insn(insn);
*r1 = (insn >> 20) & 0xf;
*x2 = (insn >> 16) & 0xf;
*b2 = (insn >> 12) & 0xf;
*d2 = insn & 0xfff;
return get_address(s, *x2, *b2, *d2);
}
static inline void decode_rs(DisasContext *s, uint64_t insn, int *r1, int *r3,
int *b2, int *d2)
{
debug_insn(insn);
*r1 = (insn >> 20) & 0xf;
/* aka m3 */
*r3 = (insn >> 16) & 0xf;
*b2 = (insn >> 12) & 0xf;
*d2 = insn & 0xfff;
}
static inline TCGv_i64 decode_si(DisasContext *s, uint64_t insn, int *i2,
int *b1, int *d1)
{
debug_insn(insn);
*i2 = (insn >> 16) & 0xff;
*b1 = (insn >> 12) & 0xf;
*d1 = insn & 0xfff;
return get_address(s, 0, *b1, *d1);
}
static inline void gen_goto_tb(DisasContext *s, int tb_num, target_ulong pc)
{
TranslationBlock *tb;
gen_update_cc_op(s);
tb = s->tb;
/* NOTE: we handle the case where the TB spans two pages here */
if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) ||
(pc & TARGET_PAGE_MASK) == ((s->pc - 1) & TARGET_PAGE_MASK)) {
/* jump to same page: we can use a direct jump */
tcg_gen_goto_tb(tb_num);
tcg_gen_movi_i64(psw_addr, pc);
tcg_gen_exit_tb((tcg_target_long)tb + tb_num);
} else {
/* jump to another page: currently not optimized */
tcg_gen_movi_i64(psw_addr, pc);
tcg_gen_exit_tb(0);
}
}
static inline void account_noninline_branch(DisasContext *s, int cc_op)
{
#ifdef DEBUG_INLINE_BRANCHES
inline_branch_miss[cc_op]++;
#endif
}
static inline void account_inline_branch(DisasContext *s)
{
#ifdef DEBUG_INLINE_BRANCHES
inline_branch_hit[s->cc_op]++;
#endif
}
static void gen_jcc(DisasContext *s, uint32_t mask, int skip)
{
TCGv_i32 tmp, tmp2, r;
TCGv_i64 tmp64;
int old_cc_op;
switch (s->cc_op) {
case CC_OP_LTGT0_32:
tmp = tcg_temp_new_i32();
tcg_gen_trunc_i64_i32(tmp, cc_dst);
switch (mask) {
case 0x8 | 0x4: /* dst <= 0 */
tcg_gen_brcondi_i32(TCG_COND_GT, tmp, 0, skip);
break;
case 0x8 | 0x2: /* dst >= 0 */
tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, skip);
break;
case 0x8: /* dst == 0 */
tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, skip);
break;
case 0x7: /* dst != 0 */
case 0x6: /* dst != 0 */
tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, skip);
break;
case 0x4: /* dst < 0 */
tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, skip);
break;
case 0x2: /* dst > 0 */
tcg_gen_brcondi_i32(TCG_COND_LE, tmp, 0, skip);
break;
default:
tcg_temp_free_i32(tmp);
goto do_dynamic;
}
account_inline_branch(s);
tcg_temp_free_i32(tmp);
break;
case CC_OP_LTGT0_64:
switch (mask) {
case 0x8 | 0x4: /* dst <= 0 */
tcg_gen_brcondi_i64(TCG_COND_GT, cc_dst, 0, skip);
break;
case 0x8 | 0x2: /* dst >= 0 */
tcg_gen_brcondi_i64(TCG_COND_LT, cc_dst, 0, skip);
break;
case 0x8: /* dst == 0 */
tcg_gen_brcondi_i64(TCG_COND_NE, cc_dst, 0, skip);
break;
case 0x7: /* dst != 0 */
case 0x6: /* dst != 0 */
tcg_gen_brcondi_i64(TCG_COND_EQ, cc_dst, 0, skip);
break;
case 0x4: /* dst < 0 */
tcg_gen_brcondi_i64(TCG_COND_GE, cc_dst, 0, skip);
break;
case 0x2: /* dst > 0 */
tcg_gen_brcondi_i64(TCG_COND_LE, cc_dst, 0, skip);
break;
default:
goto do_dynamic;
}
account_inline_branch(s);
break;
case CC_OP_LTGT_32:
tmp = tcg_temp_new_i32();
tmp2 = tcg_temp_new_i32();
tcg_gen_trunc_i64_i32(tmp, cc_src);
tcg_gen_trunc_i64_i32(tmp2, cc_dst);
switch (mask) {
case 0x8 | 0x4: /* src <= dst */
tcg_gen_brcond_i32(TCG_COND_GT, tmp, tmp2, skip);
break;
case 0x8 | 0x2: /* src >= dst */
tcg_gen_brcond_i32(TCG_COND_LT, tmp, tmp2, skip);
break;
case 0x8: /* src == dst */
tcg_gen_brcond_i32(TCG_COND_NE, tmp, tmp2, skip);
break;
case 0x7: /* src != dst */
case 0x6: /* src != dst */
tcg_gen_brcond_i32(TCG_COND_EQ, tmp, tmp2, skip);
break;
case 0x4: /* src < dst */
tcg_gen_brcond_i32(TCG_COND_GE, tmp, tmp2, skip);
break;
case 0x2: /* src > dst */
tcg_gen_brcond_i32(TCG_COND_LE, tmp, tmp2, skip);
break;
default:
tcg_temp_free_i32(tmp);
tcg_temp_free_i32(tmp2);
goto do_dynamic;
}
account_inline_branch(s);
tcg_temp_free_i32(tmp);
tcg_temp_free_i32(tmp2);
break;
case CC_OP_LTGT_64:
switch (mask) {
case 0x8 | 0x4: /* src <= dst */
tcg_gen_brcond_i64(TCG_COND_GT, cc_src, cc_dst, skip);
break;
case 0x8 | 0x2: /* src >= dst */
tcg_gen_brcond_i64(TCG_COND_LT, cc_src, cc_dst, skip);
break;
case 0x8: /* src == dst */
tcg_gen_brcond_i64(TCG_COND_NE, cc_src, cc_dst, skip);
break;
case 0x7: /* src != dst */
case 0x6: /* src != dst */
tcg_gen_brcond_i64(TCG_COND_EQ, cc_src, cc_dst, skip);
break;
case 0x4: /* src < dst */
tcg_gen_brcond_i64(TCG_COND_GE, cc_src, cc_dst, skip);
break;
case 0x2: /* src > dst */
tcg_gen_brcond_i64(TCG_COND_LE, cc_src, cc_dst, skip);
break;
default:
goto do_dynamic;
}
account_inline_branch(s);
break;
case CC_OP_LTUGTU_32:
tmp = tcg_temp_new_i32();
tmp2 = tcg_temp_new_i32();
tcg_gen_trunc_i64_i32(tmp, cc_src);
tcg_gen_trunc_i64_i32(tmp2, cc_dst);
switch (mask) {
case 0x8 | 0x4: /* src <= dst */
tcg_gen_brcond_i32(TCG_COND_GTU, tmp, tmp2, skip);
break;
case 0x8 | 0x2: /* src >= dst */
tcg_gen_brcond_i32(TCG_COND_LTU, tmp, tmp2, skip);
break;
case 0x8: /* src == dst */
tcg_gen_brcond_i32(TCG_COND_NE, tmp, tmp2, skip);
break;
case 0x7: /* src != dst */
case 0x6: /* src != dst */
tcg_gen_brcond_i32(TCG_COND_EQ, tmp, tmp2, skip);
break;
case 0x4: /* src < dst */
tcg_gen_brcond_i32(TCG_COND_GEU, tmp, tmp2, skip);
break;
case 0x2: /* src > dst */
tcg_gen_brcond_i32(TCG_COND_LEU, tmp, tmp2, skip);
break;
default:
tcg_temp_free_i32(tmp);
tcg_temp_free_i32(tmp2);