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ppc-dis.c
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ppc-dis.c
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/* ppc-dis.c -- Disassemble PowerPC instructions
Copyright 1994 Free Software Foundation, Inc.
Written by Ian Lance Taylor, Cygnus Support
This file is part of GDB, GAS, and the GNU binutils.
GDB, GAS, and the GNU binutils are free software; you can redistribute
them and/or modify them under the terms of the GNU General Public
License as published by the Free Software Foundation; either version
2, or (at your option) any later version.
GDB, GAS, and the GNU binutils are distributed in the hope that they
will be useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING. If not, write to the Free
Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#include "dis-asm.h"
/* ppc.h -- Header file for PowerPC opcode table
Copyright 1994 Free Software Foundation, Inc.
Written by Ian Lance Taylor, Cygnus Support
This file is part of GDB, GAS, and the GNU binutils.
GDB, GAS, and the GNU binutils are free software; you can redistribute
them and/or modify them under the terms of the GNU General Public
License as published by the Free Software Foundation; either version
1, or (at your option) any later version.
GDB, GAS, and the GNU binutils are distributed in the hope that they
will be useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING. If not, write to the Free
Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
/* The opcode table is an array of struct powerpc_opcode. */
struct powerpc_opcode
{
/* The opcode name. */
const char *name;
/* The opcode itself. Those bits which will be filled in with
operands are zeroes. */
uint32_t opcode;
/* The opcode mask. This is used by the disassembler. This is a
mask containing ones indicating those bits which must match the
opcode field, and zeroes indicating those bits which need not
match (and are presumably filled in by operands). */
uint32_t mask;
/* One bit flags for the opcode. These are used to indicate which
specific processors support the instructions. The defined values
are listed below. */
uint32_t flags;
/* An array of operand codes. Each code is an index into the
operand table. They appear in the order which the operands must
appear in assembly code, and are terminated by a zero. */
unsigned char operands[8];
};
/* The table itself is sorted by major opcode number, and is otherwise
in the order in which the disassembler should consider
instructions. */
extern const struct powerpc_opcode powerpc_opcodes[];
extern const int powerpc_num_opcodes;
/* Values defined for the flags field of a struct powerpc_opcode. */
/* Opcode is defined for the PowerPC architecture. */
#define PPC_OPCODE_PPC (01)
/* Opcode is defined for the POWER (RS/6000) architecture. */
#define PPC_OPCODE_POWER (02)
/* Opcode is defined for the POWER2 (Rios 2) architecture. */
#define PPC_OPCODE_POWER2 (04)
/* Opcode is only defined on 32 bit architectures. */
#define PPC_OPCODE_32 (010)
/* Opcode is only defined on 64 bit architectures. */
#define PPC_OPCODE_64 (020)
/* Opcode is supported by the Motorola PowerPC 601 processor. The 601
is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
but it also supports many additional POWER instructions. */
#define PPC_OPCODE_601 (040)
/* A macro to extract the major opcode from an instruction. */
#define PPC_OP(i) (((i) >> 26) & 0x3f)
/* The operands table is an array of struct powerpc_operand. */
struct powerpc_operand
{
/* The number of bits in the operand. */
int bits;
/* How far the operand is left shifted in the instruction. */
int shift;
/* Insertion function. This is used by the assembler. To insert an
operand value into an instruction, check this field.
If it is NULL, execute
i |= (op & ((1 << o->bits) - 1)) << o->shift;
(i is the instruction which we are filling in, o is a pointer to
this structure, and op is the opcode value; this assumes twos
complement arithmetic).
If this field is not NULL, then simply call it with the
instruction and the operand value. It will return the new value
of the instruction. If the ERRMSG argument is not NULL, then if
the operand value is illegal, *ERRMSG will be set to a warning
string (the operand will be inserted in any case). If the
operand value is legal, *ERRMSG will be unchanged (most operands
can accept any value). */
unsigned long (*insert)(uint32_t instruction, int32_t op,
const char **errmsg);
/* Extraction function. This is used by the disassembler. To
extract this operand type from an instruction, check this field.
If it is NULL, compute
op = ((i) >> o->shift) & ((1 << o->bits) - 1);
if ((o->flags & PPC_OPERAND_SIGNED) != 0
&& (op & (1 << (o->bits - 1))) != 0)
op -= 1 << o->bits;
(i is the instruction, o is a pointer to this structure, and op
is the result; this assumes twos complement arithmetic).
If this field is not NULL, then simply call it with the
instruction value. It will return the value of the operand. If
the INVALID argument is not NULL, *INVALID will be set to
non-zero if this operand type can not actually be extracted from
this operand (i.e., the instruction does not match). If the
operand is valid, *INVALID will not be changed. */
long (*extract) (uint32_t instruction, int *invalid);
/* One bit syntax flags. */
uint32_t flags;
};
/* Elements in the table are retrieved by indexing with values from
the operands field of the powerpc_opcodes table. */
extern const struct powerpc_operand powerpc_operands[];
/* Values defined for the flags field of a struct powerpc_operand. */
/* This operand takes signed values. */
#define PPC_OPERAND_SIGNED (01)
/* This operand takes signed values, but also accepts a full positive
range of values when running in 32 bit mode. That is, if bits is
16, it takes any value from -0x8000 to 0xffff. In 64 bit mode,
this flag is ignored. */
#define PPC_OPERAND_SIGNOPT (02)
/* This operand does not actually exist in the assembler input. This
is used to support extended mnemonics such as mr, for which two
operands fields are identical. The assembler should call the
insert function with any op value. The disassembler should call
the extract function, ignore the return value, and check the value
placed in the valid argument. */
#define PPC_OPERAND_FAKE (04)
/* The next operand should be wrapped in parentheses rather than
separated from this one by a comma. This is used for the load and
store instructions which want their operands to look like
reg,displacement(reg)
*/
#define PPC_OPERAND_PARENS (010)
/* This operand may use the symbolic names for the CR fields, which
are
lt 0 gt 1 eq 2 so 3 un 3
cr0 0 cr1 1 cr2 2 cr3 3
cr4 4 cr5 5 cr6 6 cr7 7
These may be combined arithmetically, as in cr2*4+gt. These are
only supported on the PowerPC, not the POWER. */
#define PPC_OPERAND_CR (020)
/* This operand names a register. The disassembler uses this to print
register names with a leading 'r'. */
#define PPC_OPERAND_GPR (040)
/* This operand names a floating point register. The disassembler
prints these with a leading 'f'. */
#define PPC_OPERAND_FPR (0100)
/* This operand is a relative branch displacement. The disassembler
prints these symbolically if possible. */
#define PPC_OPERAND_RELATIVE (0200)
/* This operand is an absolute branch address. The disassembler
prints these symbolically if possible. */
#define PPC_OPERAND_ABSOLUTE (0400)
/* This operand is optional, and is zero if omitted. This is used for
the optional BF and L fields in the comparison instructions. The
assembler must count the number of operands remaining on the line,
and the number of operands remaining for the opcode, and decide
whether this operand is present or not. The disassembler should
print this operand out only if it is not zero. */
#define PPC_OPERAND_OPTIONAL (01000)
/* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand
is omitted, then for the next operand use this operand value plus
1, ignoring the next operand field for the opcode. This wretched
hack is needed because the Power rotate instructions can take
either 4 or 5 operands. The disassembler should print this operand
out regardless of the PPC_OPERAND_OPTIONAL field. */
#define PPC_OPERAND_NEXT (02000)
/* This operand should be regarded as a negative number for the
purposes of overflow checking (i.e., the normal most negative
number is disallowed and one more than the normal most positive
number is allowed). This flag will only be set for a signed
operand. */
#define PPC_OPERAND_NEGATIVE (04000)
/* The POWER and PowerPC assemblers use a few macros. We keep them
with the operands table for simplicity. The macro table is an
array of struct powerpc_macro. */
struct powerpc_macro
{
/* The macro name. */
const char *name;
/* The number of operands the macro takes. */
unsigned int operands;
/* One bit flags for the opcode. These are used to indicate which
specific processors support the instructions. The values are the
same as those for the struct powerpc_opcode flags field. */
uint32_t flags;
/* A format string to turn the macro into a normal instruction.
Each %N in the string is replaced with operand number N (zero
based). */
const char *format;
};
extern const struct powerpc_macro powerpc_macros[];
extern const int powerpc_num_macros;
/* ppc-opc.c -- PowerPC opcode list
Copyright 1994 Free Software Foundation, Inc.
Written by Ian Lance Taylor, Cygnus Support
This file is part of GDB, GAS, and the GNU binutils.
GDB, GAS, and the GNU binutils are free software; you can redistribute
them and/or modify them under the terms of the GNU General Public
License as published by the Free Software Foundation; either version
2, or (at your option) any later version.
GDB, GAS, and the GNU binutils are distributed in the hope that they
will be useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING. If not, write to the Free
Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
/* This file holds the PowerPC opcode table. The opcode table
includes almost all of the extended instruction mnemonics. This
permits the disassembler to use them, and simplifies the assembler
logic, at the cost of increasing the table size. The table is
strictly constant data, so the compiler should be able to put it in
the .text section.
This file also holds the operand table. All knowledge about
inserting operands into instructions and vice-versa is kept in this
file. */
/* Local insertion and extraction functions. */
static unsigned long insert_bat (uint32_t, int32_t, const char **);
static long extract_bat(uint32_t, int *);
static unsigned long insert_bba(uint32_t, int32_t, const char **);
static long extract_bba(uint32_t, int *);
static unsigned long insert_bd(uint32_t, int32_t, const char **);
static long extract_bd(uint32_t, int *);
static unsigned long insert_bdm(uint32_t, int32_t, const char **);
static long extract_bdm(uint32_t, int *);
static unsigned long insert_bdp(uint32_t, int32_t, const char **);
static long extract_bdp(uint32_t, int *);
static unsigned long insert_bo(uint32_t, int32_t, const char **);
static long extract_bo(uint32_t, int *);
static unsigned long insert_boe(uint32_t, int32_t, const char **);
static long extract_boe(uint32_t, int *);
static unsigned long insert_ds(uint32_t, int32_t, const char **);
static long extract_ds(uint32_t, int *);
static unsigned long insert_li(uint32_t, int32_t, const char **);
static long extract_li(uint32_t, int *);
static unsigned long insert_mbe(uint32_t, int32_t, const char **);
static long extract_mbe(uint32_t, int *);
static unsigned long insert_mb6(uint32_t, int32_t, const char **);
static long extract_mb6(uint32_t, int *);
static unsigned long insert_nb(uint32_t, int32_t, const char **);
static long extract_nb(uint32_t, int *);
static unsigned long insert_nsi(uint32_t, int32_t, const char **);
static long extract_nsi(uint32_t, int *);
static unsigned long insert_ral(uint32_t, int32_t, const char **);
static unsigned long insert_ram(uint32_t, int32_t, const char **);
static unsigned long insert_ras(uint32_t, int32_t, const char **);
static unsigned long insert_rbs(uint32_t, int32_t, const char **);
static long extract_rbs(uint32_t, int *);
static unsigned long insert_sh6(uint32_t, int32_t, const char **);
static long extract_sh6(uint32_t, int *);
static unsigned long insert_spr(uint32_t, int32_t, const char **);
static long extract_spr(uint32_t, int *);
static unsigned long insert_tbr(uint32_t, int32_t, const char **);
static long extract_tbr(uint32_t, int *);
/* The operands table.
The fields are bits, shift, signed, insert, extract, flags. */
const struct powerpc_operand powerpc_operands[] =
{
/* The zero index is used to indicate the end of the list of
operands. */
#define UNUSED (0)
{ 0, 0, 0, 0, 0 },
/* The BA field in an XL form instruction. */
#define BA (1)
#define BA_MASK (0x1f << 16)
{ 5, 16, 0, 0, PPC_OPERAND_CR },
/* The BA field in an XL form instruction when it must be the same
as the BT field in the same instruction. */
#define BAT (2)
{ 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
/* The BB field in an XL form instruction. */
#define BB (3)
#define BB_MASK (0x1f << 11)
{ 5, 11, 0, 0, PPC_OPERAND_CR },
/* The BB field in an XL form instruction when it must be the same
as the BA field in the same instruction. */
#define BBA (4)
{ 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
/* The BD field in a B form instruction. The lower two bits are
forced to zero. */
#define BD (5)
{ 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
/* The BD field in a B form instruction when absolute addressing is
used. */
#define BDA (6)
{ 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
/* The BD field in a B form instruction when the - modifier is used.
This sets the y bit of the BO field appropriately. */
#define BDM (7)
{ 16, 0, insert_bdm, extract_bdm,
PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
/* The BD field in a B form instruction when the - modifier is used
and absolute address is used. */
#define BDMA (8)
{ 16, 0, insert_bdm, extract_bdm,
PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
/* The BD field in a B form instruction when the + modifier is used.
This sets the y bit of the BO field appropriately. */
#define BDP (9)
{ 16, 0, insert_bdp, extract_bdp,
PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
/* The BD field in a B form instruction when the + modifier is used
and absolute addressing is used. */
#define BDPA (10)
{ 16, 0, insert_bdp, extract_bdp,
PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
/* The BF field in an X or XL form instruction. */
#define BF (11)
{ 3, 23, 0, 0, PPC_OPERAND_CR },
/* An optional BF field. This is used for comparison instructions,
in which an omitted BF field is taken as zero. */
#define OBF (12)
{ 3, 23, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
/* The BFA field in an X or XL form instruction. */
#define BFA (13)
{ 3, 18, 0, 0, PPC_OPERAND_CR },
/* The BI field in a B form or XL form instruction. */
#define BI (14)
#define BI_MASK (0x1f << 16)
{ 5, 16, 0, 0, PPC_OPERAND_CR },
/* The BO field in a B form instruction. Certain values are
illegal. */
#define BO (15)
#define BO_MASK (0x1f << 21)
{ 5, 21, insert_bo, extract_bo, 0 },
/* The BO field in a B form instruction when the + or - modifier is
used. This is like the BO field, but it must be even. */
#define BOE (16)
{ 5, 21, insert_boe, extract_boe, 0 },
/* The BT field in an X or XL form instruction. */
#define BT (17)
{ 5, 21, 0, 0, PPC_OPERAND_CR },
/* The condition register number portion of the BI field in a B form
or XL form instruction. This is used for the extended
conditional branch mnemonics, which set the lower two bits of the
BI field. This field is optional. */
#define CR (18)
{ 3, 18, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
/* The D field in a D form instruction. This is a displacement off
a register, and implies that the next operand is a register in
parentheses. */
#define D (19)
{ 16, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
/* The DS field in a DS form instruction. This is like D, but the
lower two bits are forced to zero. */
#define DS (20)
{ 16, 0, insert_ds, extract_ds, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
/* The FL1 field in a POWER SC form instruction. */
#define FL1 (21)
{ 4, 12, 0, 0, 0 },
/* The FL2 field in a POWER SC form instruction. */
#define FL2 (22)
{ 3, 2, 0, 0, 0 },
/* The FLM field in an XFL form instruction. */
#define FLM (23)
{ 8, 17, 0, 0, 0 },
/* The FRA field in an X or A form instruction. */
#define FRA (24)
#define FRA_MASK (0x1f << 16)
{ 5, 16, 0, 0, PPC_OPERAND_FPR },
/* The FRB field in an X or A form instruction. */
#define FRB (25)
#define FRB_MASK (0x1f << 11)
{ 5, 11, 0, 0, PPC_OPERAND_FPR },
/* The FRC field in an A form instruction. */
#define FRC (26)
#define FRC_MASK (0x1f << 6)
{ 5, 6, 0, 0, PPC_OPERAND_FPR },
/* The FRS field in an X form instruction or the FRT field in a D, X
or A form instruction. */
#define FRS (27)
#define FRT (FRS)
{ 5, 21, 0, 0, PPC_OPERAND_FPR },
/* The FXM field in an XFX instruction. */
#define FXM (28)
#define FXM_MASK (0xff << 12)
{ 8, 12, 0, 0, 0 },
/* The L field in a D or X form instruction. */
#define L (29)
{ 1, 21, 0, 0, PPC_OPERAND_OPTIONAL },
/* The LEV field in a POWER SC form instruction. */
#define LEV (30)
{ 7, 5, 0, 0, 0 },
/* The LI field in an I form instruction. The lower two bits are
forced to zero. */
#define LI (31)
{ 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
/* The LI field in an I form instruction when used as an absolute
address. */
#define LIA (32)
{ 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
/* The MB field in an M form instruction. */
#define MB (33)
#define MB_MASK (0x1f << 6)
{ 5, 6, 0, 0, 0 },
/* The ME field in an M form instruction. */
#define ME (34)
#define ME_MASK (0x1f << 1)
{ 5, 1, 0, 0, 0 },
/* The MB and ME fields in an M form instruction expressed a single
operand which is a bitmask indicating which bits to select. This
is a two operand form using PPC_OPERAND_NEXT. See the
description in opcode/ppc.h for what this means. */
#define MBE (35)
{ 5, 6, 0, 0, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
{ 32, 0, insert_mbe, extract_mbe, 0 },
/* The MB or ME field in an MD or MDS form instruction. The high
bit is wrapped to the low end. */
#define MB6 (37)
#define ME6 (MB6)
#define MB6_MASK (0x3f << 5)
{ 6, 5, insert_mb6, extract_mb6, 0 },
/* The NB field in an X form instruction. The value 32 is stored as
0. */
#define NB (38)
{ 6, 11, insert_nb, extract_nb, 0 },
/* The NSI field in a D form instruction. This is the same as the
SI field, only negated. */
#define NSI (39)
{ 16, 0, insert_nsi, extract_nsi,
PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
/* The RA field in an D, DS, X, XO, M, or MDS form instruction. */
#define RA (40)
#define RA_MASK (0x1f << 16)
{ 5, 16, 0, 0, PPC_OPERAND_GPR },
/* The RA field in a D or X form instruction which is an updating
load, which means that the RA field may not be zero and may not
equal the RT field. */
#define RAL (41)
{ 5, 16, insert_ral, 0, PPC_OPERAND_GPR },
/* The RA field in an lmw instruction, which has special value
restrictions. */
#define RAM (42)
{ 5, 16, insert_ram, 0, PPC_OPERAND_GPR },
/* The RA field in a D or X form instruction which is an updating
store or an updating floating point load, which means that the RA
field may not be zero. */
#define RAS (43)
{ 5, 16, insert_ras, 0, PPC_OPERAND_GPR },
/* The RB field in an X, XO, M, or MDS form instruction. */
#define RB (44)
#define RB_MASK (0x1f << 11)
{ 5, 11, 0, 0, PPC_OPERAND_GPR },
/* The RB field in an X form instruction when it must be the same as
the RS field in the instruction. This is used for extended
mnemonics like mr. */
#define RBS (45)
{ 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
/* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
instruction or the RT field in a D, DS, X, XFX or XO form
instruction. */
#define RS (46)
#define RT (RS)
#define RT_MASK (0x1f << 21)
{ 5, 21, 0, 0, PPC_OPERAND_GPR },
/* The SH field in an X or M form instruction. */
#define SH (47)
#define SH_MASK (0x1f << 11)
{ 5, 11, 0, 0, 0 },
/* The SH field in an MD form instruction. This is split. */
#define SH6 (48)
#define SH6_MASK ((0x1f << 11) | (1 << 1))
{ 6, 1, insert_sh6, extract_sh6, 0 },
/* The SI field in a D form instruction. */
#define SI (49)
{ 16, 0, 0, 0, PPC_OPERAND_SIGNED },
/* The SI field in a D form instruction when we accept a wide range
of positive values. */
#define SISIGNOPT (50)
{ 16, 0, 0, 0, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
/* The SPR field in an XFX form instruction. This is flipped--the
lower 5 bits are stored in the upper 5 and vice- versa. */
#define SPR (51)
#define SPR_MASK (0x3ff << 11)
{ 10, 11, insert_spr, extract_spr, 0 },
/* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
#define SPRBAT (52)
#define SPRBAT_MASK (0x3 << 17)
{ 2, 17, 0, 0, 0 },
/* The SPRG register number in an XFX form m[ft]sprg instruction. */
#define SPRG (53)
#define SPRG_MASK (0x3 << 16)
{ 2, 16, 0, 0, 0 },
/* The SR field in an X form instruction. */
#define SR (54)
{ 4, 16, 0, 0, 0 },
/* The SV field in a POWER SC form instruction. */
#define SV (55)
{ 14, 2, 0, 0, 0 },
/* The TBR field in an XFX form instruction. This is like the SPR
field, but it is optional. */
#define TBR (56)
{ 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
/* The TO field in a D or X form instruction. */
#define TO (57)
#define TO_MASK (0x1f << 21)
{ 5, 21, 0, 0, 0 },
/* The U field in an X form instruction. */
#define U (58)
{ 4, 12, 0, 0, 0 },
/* The UI field in a D form instruction. */
#define UI (59)
{ 16, 0, 0, 0, 0 },
};
/* The functions used to insert and extract complicated operands. */
/* The BA field in an XL form instruction when it must be the same as
the BT field in the same instruction. This operand is marked FAKE.
The insertion function just copies the BT field into the BA field,
and the extraction function just checks that the fields are the
same. */
/*ARGSUSED*/
static unsigned long
insert_bat (insn, value, errmsg)
uint32_t insn;
int32_t value;
const char **errmsg;
{
return insn | (((insn >> 21) & 0x1f) << 16);
}
static long
extract_bat (insn, invalid)
uint32_t insn;
int *invalid;
{
if (invalid != (int *) NULL
&& ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
*invalid = 1;
return 0;
}
/* The BB field in an XL form instruction when it must be the same as
the BA field in the same instruction. This operand is marked FAKE.
The insertion function just copies the BA field into the BB field,
and the extraction function just checks that the fields are the
same. */
/*ARGSUSED*/
static unsigned long
insert_bba (insn, value, errmsg)
uint32_t insn;
int32_t value;
const char **errmsg;
{
return insn | (((insn >> 16) & 0x1f) << 11);
}
static long
extract_bba (insn, invalid)
uint32_t insn;
int *invalid;
{
if (invalid != (int *) NULL
&& ((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
*invalid = 1;
return 0;
}
/* The BD field in a B form instruction. The lower two bits are
forced to zero. */
/*ARGSUSED*/
static unsigned long
insert_bd (insn, value, errmsg)
uint32_t insn;
int32_t value;
const char **errmsg;
{
return insn | (value & 0xfffc);
}
/*ARGSUSED*/
static long
extract_bd (insn, invalid)
uint32_t insn;
int *invalid;
{
if ((insn & 0x8000) != 0)
return (insn & 0xfffc) - 0x10000;
else
return insn & 0xfffc;
}
/* The BD field in a B form instruction when the - modifier is used.
This modifier means that the branch is not expected to be taken.
We must set the y bit of the BO field to 1 if the offset is
negative. When extracting, we require that the y bit be 1 and that
the offset be positive, since if the y bit is 0 we just want to
print the normal form of the instruction. */
/*ARGSUSED*/
static unsigned long
insert_bdm (insn, value, errmsg)
uint32_t insn;
int32_t value;
const char **errmsg;
{
if ((value & 0x8000) != 0)
insn |= 1 << 21;
return insn | (value & 0xfffc);
}
static long
extract_bdm (insn, invalid)
uint32_t insn;
int *invalid;
{
if (invalid != (int *) NULL
&& ((insn & (1 << 21)) == 0
|| (insn & (1 << 15)) == 0))
*invalid = 1;
if ((insn & 0x8000) != 0)
return (insn & 0xfffc) - 0x10000;
else
return insn & 0xfffc;
}
/* The BD field in a B form instruction when the + modifier is used.
This is like BDM, above, except that the branch is expected to be
taken. */
/*ARGSUSED*/
static unsigned long
insert_bdp (insn, value, errmsg)
uint32_t insn;
int32_t value;
const char **errmsg;
{
if ((value & 0x8000) == 0)
insn |= 1 << 21;
return insn | (value & 0xfffc);
}
static long
extract_bdp (insn, invalid)
uint32_t insn;
int *invalid;
{
if (invalid != (int *) NULL
&& ((insn & (1 << 21)) == 0
|| (insn & (1 << 15)) != 0))
*invalid = 1;
if ((insn & 0x8000) != 0)
return (insn & 0xfffc) - 0x10000;
else
return insn & 0xfffc;
}
/* Check for legal values of a BO field. */
static int
valid_bo (int32_t value)
{
/* Certain encodings have bits that are required to be zero. These
are (z must be zero, y may be anything):
001zy
011zy
1z00y
1z01y
1z1zz
*/
switch (value & 0x14)
{
default:
case 0:
return 1;
case 0x4:
return (value & 0x2) == 0;
case 0x10:
return (value & 0x8) == 0;
case 0x14:
return value == 0x14;
}
}
/* The BO field in a B form instruction. Warn about attempts to set
the field to an illegal value. */
static unsigned long
insert_bo (insn, value, errmsg)
uint32_t insn;
int32_t value;
const char **errmsg;
{
if (errmsg != (const char **) NULL
&& ! valid_bo (value))
*errmsg = "invalid conditional option";
return insn | ((value & 0x1f) << 21);
}
static long
extract_bo (insn, invalid)
uint32_t insn;
int *invalid;
{
int32_t value;
value = (insn >> 21) & 0x1f;
if (invalid != (int *) NULL
&& ! valid_bo (value))
*invalid = 1;
return value;
}
/* The BO field in a B form instruction when the + or - modifier is
used. This is like the BO field, but it must be even. When
extracting it, we force it to be even. */
static unsigned long
insert_boe (insn, value, errmsg)
uint32_t insn;
int32_t value;
const char **errmsg;
{
if (errmsg != (const char **) NULL)
{
if (! valid_bo (value))
*errmsg = "invalid conditional option";
else if ((value & 1) != 0)
*errmsg = "attempt to set y bit when using + or - modifier";
}
return insn | ((value & 0x1f) << 21);
}
static long
extract_boe (insn, invalid)
uint32_t insn;
int *invalid;
{
int32_t value;
value = (insn >> 21) & 0x1f;
if (invalid != (int *) NULL
&& ! valid_bo (value))
*invalid = 1;
return value & 0x1e;
}
/* The DS field in a DS form instruction. This is like D, but the
lower two bits are forced to zero. */
/*ARGSUSED*/
static unsigned long
insert_ds (insn, value, errmsg)
uint32_t insn;
int32_t value;
const char **errmsg;
{
return insn | (value & 0xfffc);
}
/*ARGSUSED*/
static long
extract_ds (insn, invalid)
uint32_t insn;
int *invalid;
{
if ((insn & 0x8000) != 0)
return (insn & 0xfffc) - 0x10000;
else
return insn & 0xfffc;
}
/* The LI field in an I form instruction. The lower two bits are
forced to zero. */
/*ARGSUSED*/
static unsigned long
insert_li (insn, value, errmsg)
uint32_t insn;
int32_t value;
const char **errmsg;
{
return insn | (value & 0x3fffffc);
}
/*ARGSUSED*/
static long
extract_li (insn, invalid)
uint32_t insn;
int *invalid;
{
if ((insn & 0x2000000) != 0)
return (insn & 0x3fffffc) - 0x4000000;
else
return insn & 0x3fffffc;
}
/* The MB and ME fields in an M form instruction expressed as a single
operand which is itself a bitmask. The extraction function always
marks it as invalid, since we never want to recognize an
instruction which uses a field of this type. */
static unsigned long
insert_mbe (insn, value, errmsg)
uint32_t insn;
int32_t value;
const char **errmsg;
{
uint32_t uval;
int mb, me;
uval = value;
if (uval == 0)
{
if (errmsg != (const char **) NULL)
*errmsg = "illegal bitmask";
return insn;
}
me = 31;
while ((uval & 1) == 0)
{
uval >>= 1;
--me;
}
mb = me;
uval >>= 1;
while ((uval & 1) != 0)
{
uval >>= 1;
--mb;
}
if (uval != 0)
{
if (errmsg != (const char **) NULL)
*errmsg = "illegal bitmask";
}
return insn | (mb << 6) | (me << 1);
}
static long
extract_mbe (insn, invalid)
uint32_t insn;
int *invalid;
{
long ret;
int mb, me;
int i;
if (invalid != (int *) NULL)
*invalid = 1;
ret = 0;
mb = (insn >> 6) & 0x1f;
me = (insn >> 1) & 0x1f;
for (i = mb; i < me; i++)
ret |= 1 << (31 - i);
return ret;
}
/* The MB or ME field in an MD or MDS form instruction. The high bit
is wrapped to the low end. */
/*ARGSUSED*/
static unsigned long
insert_mb6 (insn, value, errmsg)
uint32_t insn;
int32_t value;