Updated PC and IFID buffer

IF/PC.v

@@ -0,0 +1,15 @@
+module PC(address_in,address_out,halt,clk,reset);
+	input halt,clk,reset;
+	input [15:0] address_in;
+	output reg [15:0] address_out;
+
+	always@(posedge clk or negedge reset) begin
+		if (!reset) begin 
+			address_out<=0;
+		end else if(halt) begin
+			address_out <= 16'hFFFF;
+		end else begin
+			address_out <= address_in;
+		end
+	end
+endmodule

IF/PC_tb.v

@@ -0,0 +1,47 @@
+`timescale 1ns / 1ps
+`include "PC.v"
+
+module PC_tb();
+	reg halt,clk,reset;
+	reg [15:0] address_in;
+	wire [15:0] address_out;
+
+    PC uut(address_in,address_out,halt,clk,reset);
+
+    initial clk=0;
+	always #10 clk = ~clk;
+
+    initial begin
+		$vcdpluson;
+        // Initialize Inputs
+		halt = 0;
+		reset = 1;
+		address_in = 0;
+		#20
+		halt = 0;
+		reset = 1;
+		address_in = 2;
+		#20
+		halt = 0;
+		reset = 1;
+		address_in = 4;
+		#20
+		halt = 0;
+		reset = 0;
+		address_in = 6;
+		#20
+		halt = 0;
+		reset = 1;
+		address_in = 0;
+		#20
+		halt = 0;
+		reset = 0;
+		address_in = 2;
+		#20
+		halt = 1;
+		reset = 1;
+		address_in = 2;
+		#40	
+		$finish;
+    end
+endmodule

IFIDBuffer.v

@@ -1,30 +1,29 @@
 //on posedge clock with reset, if/id buffer
 
-module IFIDBuffer(
-	input clk, hazard, reset,
-	input[15:0] PC,
-	input[3:0] opcode, one, two, three,
-	output reg[3:0] opcode_o, one_o, two_o, three_o,
-	output reg[15:0] PC_o
-	);
+module IFIDBuffer(clk,hazard,reset,PC,opcode,one,two,three,opcode_o,one_o,two_o,three_o,PC_o);
+	input clk, hazard, reset;
+	input[3:0] opcode, one, two, three;
+	input[15:0] PC;
+	output reg[3:0] opcode_o, one_o, two_o, three_o;
+	output reg[15:0] PC_o;
 
-always @(posedge clk or negedge reset)
-begin
-	if (!reset)
+	always @(posedge clk or negedge reset)
 	begin
-		opcode_o<=4'b0000;
-		one_o<=4'b0000;
-		two_o<=4'b0000;
-		three_o<=4'b0000;
-		PC_o<=0;
+		if (!reset)
+		begin
+			opcode_o<=4'b0000;
+			one_o<=4'b0000;
+			two_o<=4'b0000;
+			three_o<=4'b0000;
+			PC_o<=0;
+		end
+		else if (!hazard)			//If FLUSH, then perform No operation
+		begin
+			opcode_o<=opcode;
+			one_o<=one;
+			two_o<=two;
+			three_o<=three;
+			PC_o<=PC;
+		end
 	end
-	else if (!hazard)			//If FLUSH, then perform No operation
-	begin
-		opcode_o<=opcode;
-		one_o<=one;
-		two_o<=two;
-		three_o<=three;
-		PC_o<=PC;
-	end
-end
 endmodule

IFIDBuffer_tb.v

@@ -0,0 +1,45 @@
+`timescale 1ns / 1ps
+`include "IFIDBuffer.v"
+
+module IFIDBuffer_tb();
+	reg clk, hazard, reset;
+	reg[3:0] opcode, one, two, three;
+	reg[15:0] PC;
+	wire[3:0] opcode_o, one_o, two_o, three_o;
+	wire[15:0] PC_o;
+
+    IFIDBuffer uut(clk,hazard,reset,PC,opcode,one,two,three,opcode_o,one_o,two_o,three_o,PC_o);
+
+    initial clk=0;
+	always #10 clk = ~clk;
+
+    initial begin
+		$vcdpluson;
+        // Initialize Inputs
+		reset = 1;
+		hazard = 0;
+		opcode = 2;
+		one = 3;
+		two = 4;
+		three = 5;
+		PC = 15;
+		#20
+		reset = 1;
+		hazard = 0;
+		opcode = 10;
+		one = 11;
+		two = 12;
+		three = 13;
+		PC = 17;
+		#20
+		reset = 0;
+		hazard = 0;
+		opcode = 10;
+		one = 11;
+		two = 12;
+		three = 13;
+		PC = 17;
+		#20
+		$finish;
+    end
+endmodule