Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Missing auto fix for signal_100, variable_100, type_100, etc #1205

Closed
maltaisn opened this issue Jul 23, 2024 · 2 comments
Closed

Missing auto fix for signal_100, variable_100, type_100, etc #1205

maltaisn opened this issue Jul 23, 2024 · 2 comments
Labels

Comments

@maltaisn
Copy link

It seems auto fix only partially works for these rules:

  • signal_100
  • type_100
  • subtype_100
  • file_100

The extra spaces are removed up until the length of constant and then it stops. So it works for constant and variable.

With the following configuration file:

rule:
  constant_101:
    disable: no
    number_of_spaces: 1
  file_100:
    disable: no
    number_of_spaces: 1
  signal_100:
    disable: no
    number_of_spaces: 1
  subtype_100:
    disable: no
    number_of_spaces: 1
  type_100:
    disable: no
    number_of_spaces: 1
  variable_100:
    disable: no
    number_of_spaces: 1
  type_010:
    disable: yes

And this file:

library ieee;
  use ieee.std_logic_1164.all;

entity b is
  port (
    a : in    std_logic
  );
end entity b;

architecture a of b is

  signal        t1 : std_logic;
  constant      t2 : std_logic := '0';
  variable      t3 : std_logic;
  file          t4 : std_logic;
  subtype       t5 is std_logic_vector(1 downto 0);
  type          t6 is array (0 to 3) of t5;

begin

end architecture a;

With vsg -c vsg.yml -f top.vhd --fix, I get the following fixed file:

library ieee;
  use ieee.std_logic_1164.all;

entity b is
  port (
    a : in    std_logic
  );
end entity b;

architecture a of b is

  signal   t1 : std_logic;
  constant t2 : std_logic := '0';
  variable t3 : std_logic;
  file     t4 : std_logic;
  subtype  t5 is std_logic_vector(1 downto 0);
  type     t6 is array (0 to 3) of t5;

begin

end architecture a;

And the output:

================================================================================
File:  top.vhd
================================================================================
Phase 2 of 7... Reporting
Total Rules Checked: 314
Total Violations:    4
  Error   :     4
  Warning :     0
----------------------------+------------+------------+--------------------------------------
  Rule                      |  severity  |  line(s)   | Solution
----------------------------+------------+------------+--------------------------------------
  signal_100                | Error      |         12 | Change the number of space(s) between signal and t1 to 1
  file_100                  | Error      |         15 | Change the number of space(s) between file and t4 to 1
  subtype_100               | Error      |         16 | Change the number of space(s) between subtype and t5 to 1
  type_100                  | Error      |         17 | Change the number of space(s) between type and t6 to 1
----------------------------+------------+------------+--------------------------------------
@maltaisn maltaisn added the bug label Jul 23, 2024
@maltaisn
Copy link
Author

This generally seems to happen whenever I specify number_of_spaces: 1.

@maltaisn
Copy link
Author

Nevermind, I must be because I forgot to disable architecture_029.

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
Projects
Status: Done
Development

No branches or pull requests

1 participant