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README.md

Carry-Lookahead Adder (CLA) Simulation

Overview

This directory contains SystemVerilog implementation and testbench for a Carry-Lookahead Adder (CLA), a fast digital circuit to perform addition. CLAs are known for their ability to calculate carry bits quickly, reducing the addition time compared to simple ripple-carry adders, especially for wider bit-widths.

Files Description

  • cla-adder.sv: The main module defines a parametrizable CLA capable of adding two N-bit numbers along with an input carry bit. The module calculates the sum and the output carry bit, showcasing the CLA's efficiency in handling carry propagation.

  • testbench_5.sv: Provides a testbench to simulate and verify the functionality of the CLA module with different bit widths (e.g., 2-bit and 8-bit). It dynamically changes input values to test various addition scenarios and monitor the correctness of the sum and carry-out outputs.

Simulation Setup

Prerequisites

  • A SystemVerilog-compatible simulator (e.g., ModelSim, VCS, Vivado Simulator).
  • Basic understanding of digital circuits and SystemVerilog syntax.

Running the Simulation

  1. Compile the cla-adder.sv and testbench_5.sv files using your simulator's compilation command or IDE.

  2. Execute the simulation by running the compiled testbench. Make sure both the CLA module and the testbench are correctly loaded and compiled.

  3. Observe the outputs (sum and carry-out) for correctness. The testbench will automatically cycle through a range of input values for both a and b inputs, along with a fixed c_in value, to ensure comprehensive testing of the CLA module.

Understanding the CLA Module

The CLA module utilizes the concept of generate and propagate to quickly determine carry bits for each bit position. This approach significantly speeds up addition by reducing the dependency on the calculation of previous carry bits:

  • Generate (g): Indicates if a carry will be generated by the two adding bits regardless of the carry-in.
  • Propagate (p): Indicates if a carry-in will be propagated as carry-out by the two adding bits.

The module calculates these terms for each bit position and uses them to efficiently compute the carry for the entire adder.

Contributing

Contributions to this CLA simulation are welcomed, including optimizations, additional features, or improved test coverage. Please feel free to fork this repository, commit your changes, and submit a pull request with a clear description of your modifications or enhancements.

License

This project is provided for educational and non-commercial use. Redistribution and use, with or without modification, are permitted provided that the original author is credited.